VHDL -- 設計 ALU

VHDL 電路設計

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處理器設計

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity alu is 
  port (A, B : in std_logic_vector(7 downto 0);
        S : in std_logic_vector(2 downto 0);
        Y : out std_logic_vector(7 downto 0));
end alu;

architecture a of alu is 
begin
  with S select 
  Y <= (A+B) when "000", 
       (A-B) when "001",
       (A and B) when "010",
       (A or B) when "011",
       not (A) when "100",
       (A xor B) when "101",
       A when others;
end a;

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