脈衝偵測電路

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脈衝偵測電路

ptd.jpg

Verilog 程式:ptd.v

`timescale 10ns/1ns

module ptd(input clk, output ppulse);

not g1(nclkd, clk);
nand g2(npulse, nclkd, clk);
not g3(ppulse, npulse);

endmodule

module main;
 reg clk;
 wire p;

 ptd ptd1(clk, p);

 initial begin
  clk = 0;
 end

 always #1 begin
   clk = clk + 1;
   $monitor("%dns monitor: clk=%b p=%d", $stime, clk, p);
 end

initial #100 $finish;

endmodule

執行結果

D:\ccc101\Verilog>iverilog ptd.v - o ptd

D:\ccc101\Verilog>vvp ptd
         1ns monitor: clk=1 p=0
         2ns monitor: clk=0 p=0
         3ns monitor: clk=1 p=0
         4ns monitor: clk=0 p=0
         5ns monitor: clk=1 p=0
         6ns monitor: clk=0 p=0
         7ns monitor: clk=1 p=0
         8ns monitor: clk=0 p=0
         9ns monitor: clk=1 p=0
        10ns monitor: clk=0 p=0
        11ns monitor: clk=1 p=0
        12ns monitor: clk=0 p=0
        13ns monitor: clk=1 p=0
        14ns monitor: clk=0 p=0
        15ns monitor: clk=1 p=0
        16ns monitor: clk=0 p=0
        17ns monitor: clk=1 p=0
        18ns monitor: clk=0 p=0
        19ns monitor: clk=1 p=0
        20ns monitor: clk=0 p=0
        21ns monitor: clk=1 p=0
        22ns monitor: clk=0 p=0
        23ns monitor: clk=1 p=0
        24ns monitor: clk=0 p=0
        25ns monitor: clk=1 p=0
        26ns monitor: clk=0 p=0
        27ns monitor: clk=1 p=0
        28ns monitor: clk=0 p=0
        29ns monitor: clk=1 p=0
        30ns monitor: clk=0 p=0
        31ns monitor: clk=1 p=0
        32ns monitor: clk=0 p=0
        33ns monitor: clk=1 p=0
        34ns monitor: clk=0 p=0
        35ns monitor: clk=1 p=0
        36ns monitor: clk=0 p=0
        37ns monitor: clk=1 p=0
        38ns monitor: clk=0 p=0
        39ns monitor: clk=1 p=0
        40ns monitor: clk=0 p=0
        41ns monitor: clk=1 p=0
        42ns monitor: clk=0 p=0
        43ns monitor: clk=1 p=0
        44ns monitor: clk=0 p=0
        45ns monitor: clk=1 p=0
        46ns monitor: clk=0 p=0
        47ns monitor: clk=1 p=0
        48ns monitor: clk=0 p=0
        49ns monitor: clk=1 p=0
        50ns monitor: clk=0 p=0
        51ns monitor: clk=1 p=0
        52ns monitor: clk=0 p=0
        53ns monitor: clk=1 p=0
        54ns monitor: clk=0 p=0
        55ns monitor: clk=1 p=0
        56ns monitor: clk=0 p=0
        57ns monitor: clk=1 p=0
        58ns monitor: clk=0 p=0
        59ns monitor: clk=1 p=0
        60ns monitor: clk=0 p=0
        61ns monitor: clk=1 p=0
        62ns monitor: clk=0 p=0
        63ns monitor: clk=1 p=0
        64ns monitor: clk=0 p=0
        65ns monitor: clk=1 p=0
        66ns monitor: clk=0 p=0
        67ns monitor: clk=1 p=0
        68ns monitor: clk=0 p=0
        69ns monitor: clk=1 p=0
        70ns monitor: clk=0 p=0
        71ns monitor: clk=1 p=0
        72ns monitor: clk=0 p=0
        73ns monitor: clk=1 p=0
        74ns monitor: clk=0 p=0
        75ns monitor: clk=1 p=0
        76ns monitor: clk=0 p=0
        77ns monitor: clk=1 p=0
        78ns monitor: clk=0 p=0
        79ns monitor: clk=1 p=0
        80ns monitor: clk=0 p=0
        81ns monitor: clk=1 p=0
        82ns monitor: clk=0 p=0
        83ns monitor: clk=1 p=0
        84ns monitor: clk=0 p=0
        85ns monitor: clk=1 p=0
        86ns monitor: clk=0 p=0
        87ns monitor: clk=1 p=0
        88ns monitor: clk=0 p=0
        89ns monitor: clk=1 p=0
        90ns monitor: clk=0 p=0
        91ns monitor: clk=1 p=0
        92ns monitor: clk=0 p=0
        93ns monitor: clk=1 p=0
        94ns monitor: clk=0 p=0
        95ns monitor: clk=1 p=0
        96ns monitor: clk=0 p=0
        97ns monitor: clk=1 p=0
        98ns monitor: clk=0 p=0
        99ns monitor: clk=1 p=0
       100ns monitor: clk=0 p=0

Icarus 執行測試

  1. 使用脈衝偵測電路設計邊緣觸發正反器
  2. 使用脈衝偵測電路設計邊緣觸發暫存器

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