# 設計方案

## 記憶體模組：memory.v

``````module memory(input clock, reset, en, r_w,
input [7:0] abus, input [7:0] dbus_in, output [7:0] dbus_out);
reg [7:0] m [0:128];
reg [7:0] data;
reg [7:0] i;

always @(posedge clock)
begin
if (reset == 1)
begin
m[0] <= 8'h00;
m[1] <= 8'h01;
m[2] <= 8'h02;
m[3] <= 8'h03;
m[4] <= 8'h04;
data = 8'h00;
end
else if (en == 1 && r_w == 0) // r_w==0:write
begin
data = dbus_in;
m[abus] = dbus_in;
end
else if (en == 1 && r_w == 1) // r_w==1:read
data = m[abus];
else
data = 8'hZZ;
end
assign dbus_out = data;
endmodule```
```

## 記憶體測試程式：memoryTest.v

```````timescale 1ns/10ps

module memoryTest;
reg clock, reset, en, r_w;
reg [7:0] data_in;
wire [7:0] dbus_out;

memory DUT (.clock(clock), .reset(reset), .en(en), .r_w(r_w),

initial // reset：設定 memory 內容為 0,1,2,....,127
begin
clock = 0;
reset = 1;
en = 0;
r_w = 1; // r_w=1:讀取模式
#75;
en = 1;
reset = 0;
#500;
r_w = 0; // 寫入模式
data_in = 8'h3A;
#100;
r_w = 1; // 讀取模式
data_in = 0;
end

always #50 clock = clock + 1;

always #200
begin
end

endmodule```
```

# 參考方案：

## 方案一

``````module ram(input clock, reset, en, r_w,
input [7:0] abus, inout [7:0] dbus);
reg [7:0] m [0:128];
reg [7:0] data;
reg [7:0] i;

always @(posedge clock)
begin
if (reset == 1)
begin
m[0] <= 8'h00;
m[1] <= 8'h01;
m[2] <= 8'h02;
m[3] <= 8'h03;
m[4] <= 8'h04;
data = 8'hZZ;
end
else if (en == 1 && r_w == 0) // r_w==0:write
begin
data = dbus;
m[abus] = dbus;
end
else if (en == 1 && r_w == 1) // r_w==1:read
data = m[abus];
else
data = 8'hZZ;
end
assign dbus = data;
endmodule```
```

```````timescale 1ns/10ps

module ramTest;
reg clock, reset, en, r_w;
wire [7:0] dbus;

ram DUT (.clock(clock), .reset(reset),

initial // reset：設定 memory 內容為 0,1,2,....,127
begin
\$display ("ramTest:initial");
clock = 0;
reset = 1;
en = 0;
r_w = 1; // r_w=1:讀取模式
#100;
en = 1;
reset = 0;
end

always #50 clock = clock + 1;

always #200
begin
end

endmodule```
```

## 方案二：

``````module mema (r_wb,addr,d_q);
inout [7:0] d_q;
reg [7:0] data [0:255];
assign d_q = (r_wb) ? data[addr] : 8'hz ;
always @(r_wb)
if (!r_wb) data[addr] = d_q ;
if (!r_wb) data[addr] = d_q ;
endmodule```
```

## 方案三：

``````module i2c_sp_ram(
//Inputs
clk,    //clock
wr_en,  //write enable
data_in,//data in

//Output
data_out//data out
);

//Parameter Declaration
parameter DEPTH = 8; //depth of FIFO
parameter  DATA_BUS_WD = 8; //data bus width

//Inputs Declarations
input  clk;                         //Clock
input  wr_en;                       //Write Enable
input  [DATA_BUS_WD-1:0] data_in;   //Data Input

//output Declarations
output [DATA_BUS_WD-1:0] data_out;  //Data Output

//reg Declarations
reg [DATA_BUS_WD-1:0] mem [DEPTH-1:0];//Memory
reg [DATA_BUS_WD-1:0] data_out;      //Data Output

//Generation of data_out
always @(posedge clk)
end
//Generation Writing data into memory
always @(posedge clk)
begin: WRITE_GEN
end

endmodule```
```

# 方案四：

``````module RamChip (Address, Data, CS, WE, OE);

parameter WordSize = 1;

inout [WordSize-1:0] Data;
input CS, WE, OE;

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};

always @(CS or WE)
if (!CS && !WE)

always @(WE or OE)
if (!WE && !OE)
\$display("Operational error in RamChip: OE and WE both active");

endmodule```
```

# 參考文獻

1. Technical Tidbits: Ram Modelling in Verilog — http://www.angelfire.com/in/rajesh52/tip2.html
2. TOPIC: verilog code for RAM and FIFO — http://www.vlsibank.com/sessionspage.asp?titl_id=8240
3. The following are some of useful verilog examples. — http://asic.co.in/Index_files/verilogexamples.htm#link49