全加器

Verilog

基本語法

型態

全域變數

基本元件

多樣的寫法

指定

assign

always

initial

運算式

分枝

迴圈

模組

函數

Task

陣列

輸出入

觀察

真值表

測試程式

訊息顯示

注意事項

模擬程序

硬體工程

程式範例

Xor

Xor3

全加器

加法器

加減器

快速加法器

乘法器

ALU

閂鎖器

脈衝偵測

計數器

多工器

暫存器群

記憶體

延遲問題

浮點數

狀態機

程式計數器

CPU0-Mini

CPU0

pipeline

工具

QuartusII

Icarus

Veritek

訊息

相關網站

參考文獻

最新修改

簡體版

English

程式:fulladder.v

module fulladder (input a, b, c_in, output sum, c_out);
wire s1, c1, c2;

xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
or g5(c_out, c2, c1) ;

endmodule

module fulladder_test;
reg a, b, c_in;
wire sum, c_out;

fulladder DUT (a, b, c_in, sum, c_out);

initial
begin
  a = 0;
  b = 0;
  c_in = 0;
end

always #50 begin
  a = a+1;
  $monitor("%4dns monitor: a=%d b=%d c_in=%d sum=%d c_out=%d", 
           $stime, a, b, c_in, sum, c_out);
end

always #100 begin
  b = b+1;
end

always #200 begin
  c_in = c_in+1;
end

initial #2000 $finish;

endmodule

Icarus 執行結果

D:\ccc101\icarus\ccc>iverilog -o fulladder fulladder.v

D:\ccc101\icarus\ccc>vvp fulladder
  50ns monitor: a=1 b=0 c_in=0 sum=1 c_out=0
 100ns monitor: a=0 b=1 c_in=0 sum=1 c_out=0
 150ns monitor: a=1 b=1 c_in=0 sum=0 c_out=1
 200ns monitor: a=0 b=0 c_in=1 sum=1 c_out=0
 250ns monitor: a=1 b=0 c_in=1 sum=0 c_out=1
 300ns monitor: a=0 b=1 c_in=1 sum=0 c_out=1
 350ns monitor: a=1 b=1 c_in=1 sum=1 c_out=1
 400ns monitor: a=0 b=0 c_in=0 sum=0 c_out=0
 450ns monitor: a=1 b=0 c_in=0 sum=1 c_out=0
 500ns monitor: a=0 b=1 c_in=0 sum=1 c_out=0
 550ns monitor: a=1 b=1 c_in=0 sum=0 c_out=1
 600ns monitor: a=0 b=0 c_in=1 sum=1 c_out=0
 650ns monitor: a=1 b=0 c_in=1 sum=0 c_out=1
 700ns monitor: a=0 b=1 c_in=1 sum=0 c_out=1
 750ns monitor: a=1 b=1 c_in=1 sum=1 c_out=1
 800ns monitor: a=0 b=0 c_in=0 sum=0 c_out=0
 850ns monitor: a=1 b=0 c_in=0 sum=1 c_out=0
 900ns monitor: a=0 b=1 c_in=0 sum=1 c_out=0
 950ns monitor: a=1 b=1 c_in=0 sum=0 c_out=1
1000ns monitor: a=0 b=0 c_in=1 sum=1 c_out=0
1050ns monitor: a=1 b=0 c_in=1 sum=0 c_out=1
1100ns monitor: a=0 b=1 c_in=1 sum=0 c_out=1
1150ns monitor: a=1 b=1 c_in=1 sum=1 c_out=1
1200ns monitor: a=0 b=0 c_in=0 sum=0 c_out=0
1250ns monitor: a=1 b=0 c_in=0 sum=1 c_out=0
1300ns monitor: a=0 b=1 c_in=0 sum=1 c_out=0
1350ns monitor: a=1 b=1 c_in=0 sum=0 c_out=1
1400ns monitor: a=0 b=0 c_in=1 sum=1 c_out=0
1450ns monitor: a=1 b=0 c_in=1 sum=0 c_out=1
1500ns monitor: a=0 b=1 c_in=1 sum=0 c_out=1
1550ns monitor: a=1 b=1 c_in=1 sum=1 c_out=1
1600ns monitor: a=0 b=0 c_in=0 sum=0 c_out=0
1650ns monitor: a=1 b=0 c_in=0 sum=1 c_out=0
1700ns monitor: a=0 b=1 c_in=0 sum=1 c_out=0
1750ns monitor: a=1 b=1 c_in=0 sum=0 c_out=1
1800ns monitor: a=0 b=0 c_in=1 sum=1 c_out=0
1850ns monitor: a=1 b=0 c_in=1 sum=0 c_out=1
1900ns monitor: a=0 b=1 c_in=1 sum=0 c_out=1
1950ns monitor: a=1 b=1 c_in=1 sum=1 c_out=1
2000ns monitor: a=0 b=0 c_in=0 sum=0 c_out=0

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