# 4 位元進位前瞻快速加法器

``````module CLA_4bit(output [3:0] S, output Cout,PG,GG, input [3:0] A,B, input Cin);
wire [3:0] G,P,C;

assign G = A & B; //Generate
assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0]&C[0]);
assign C[2] = G[1] | (P[1]&G[0]) | (P[1]&P[0]&C[0]);
assign C[3] = G[2] | (P[2]&G[1]) | (P[2]&P[1]&G[0]) | (P[2]&P[1]&P[0]&C[0]);
assign Cout = G[3] | (P[3]&G[2]) | (P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0])
|(P[3]&P[2]&P[1]&P[0]&C[0]);
assign S = P ^ C;
assign PG = P[3] & P[2] & P[1] & P[0];
assign GG = G[3] | (P[3]&G[2]) | (P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]);

endmodule```
```

## 參考文獻

1. 4 Bit Carry Look Ahead Adder in Verilog, JeyaTech, Exploring Fundamentals, Wednesday, February 29, 2012
3. Structural 16bit CLA adder in Verilog, A whole 16 bit adder, Tuesday, September 25, 2007

# 使用 Verilog 撰寫加法器

## 最基本加法器

``````module adder(input  [7:0] a, input  [7:0] b, output [8:0] sum);
assign sum = a + b;
endmodule```
```

# 加入前後暫存器以減低延遲

``````module adder(input clock, input nreset, input [7:0] a, input [7:0] b, output reg [8:0] sum);
reg [7:0] ta, tb;
always@(posedge clock, negedge nreset) begin
if (!nreset) begin
ta    <= 0;
tb    <= 0;
sum <= 0;
end
else begin
a    <= ta;
b    <= tb;
sum <= a + b;
end
end
endmodule```
```