Falu

Verilog

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參考文獻

最新修改

簡體版

English

程式:falu.v

module main;
 reg  [1:0] op;
 real ra, rb, ry;

 initial begin
  ra = 3.14;
  rb = 50*50;
  op = 2'b00;
 end

 always #50 begin
   op = op + 1;
  case(op)
    2'b00: ry = ra + rb;
    2'b01: ry = ra - rb;
    2'b10: ry = ra * rb;
    2'b11: ry = ra / rb;
  endcase
   $monitor("%dns monitor: op=%b a=%f b=%f y=%f", $stime, op, ra, rb, ry);
end

initial #1000 $finish;

endmodule

執行結果

D:\oc>iverilog falu.v -o falu

D:\oc>vvp falu
        50ns monitor: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       100ns monitor: op=10 a=3.140000 b=2500.000000 y=7850.000000
       150ns monitor: op=11 a=3.140000 b=2500.000000 y=0.001256
       200ns monitor: op=00 a=3.140000 b=2500.000000 y=2503.140000
       250ns monitor: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       300ns monitor: op=10 a=3.140000 b=2500.000000 y=7850.000000
       350ns monitor: op=11 a=3.140000 b=2500.000000 y=0.001256
       400ns monitor: op=00 a=3.140000 b=2500.000000 y=2503.140000
       450ns monitor: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       500ns monitor: op=10 a=3.140000 b=2500.000000 y=7850.000000
       550ns monitor: op=11 a=3.140000 b=2500.000000 y=0.001256
       600ns monitor: op=00 a=3.140000 b=2500.000000 y=2503.140000
       650ns monitor: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       700ns monitor: op=10 a=3.140000 b=2500.000000 y=7850.000000
       750ns monitor: op=11 a=3.140000 b=2500.000000 y=0.001256
       800ns monitor: op=00 a=3.140000 b=2500.000000 y=2503.140000
       850ns monitor: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       900ns monitor: op=10 a=3.140000 b=2500.000000 y=7850.000000
       950ns monitor: op=11 a=3.140000 b=2500.000000 y=0.001256
      1000ns monitor: op=00 a=3.140000 b=2500.000000 y=2503.140000

修改用 task 後

module main;
 reg  [1:0] op;
 real a, b, y;

task falu;
begin
  case (op)
    2'b00: y = a + b;
    2'b01: y = a - b;
    2'b10: y = a * b;
    2'b11: y = a / b;
  endcase
end
endtask

 initial begin
  a = 3.14;
  b = 50*50;
  op = 2'b00;
 end

 always #50 begin
   op = op + 1;
   falu();
   $display("%dns: op=%b a=%f b=%f y=%f", $stime, op, a, b, y);
end

initial #1000 $finish;

endmodule

執行結果

D:\oc>iverilog falu.v -o falu

D:\oc>vvp falu
        50ns: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       100ns: op=10 a=3.140000 b=2500.000000 y=7850.000000
       150ns: op=11 a=3.140000 b=2500.000000 y=0.001256
       200ns: op=00 a=3.140000 b=2500.000000 y=2503.140000
       250ns: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       300ns: op=10 a=3.140000 b=2500.000000 y=7850.000000
       350ns: op=11 a=3.140000 b=2500.000000 y=0.001256
       400ns: op=00 a=3.140000 b=2500.000000 y=2503.140000
       450ns: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       500ns: op=10 a=3.140000 b=2500.000000 y=7850.000000
       550ns: op=11 a=3.140000 b=2500.000000 y=0.001256
       600ns: op=00 a=3.140000 b=2500.000000 y=2503.140000
       650ns: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       700ns: op=10 a=3.140000 b=2500.000000 y=7850.000000
       750ns: op=11 a=3.140000 b=2500.000000 y=0.001256
       800ns: op=00 a=3.140000 b=2500.000000 y=2503.140000
       850ns: op=01 a=3.140000 b=2500.000000 y=-2496.860000
       900ns: op=10 a=3.140000 b=2500.000000 y=7850.000000
       950ns: op=11 a=3.140000 b=2500.000000 y=0.001256
      1000ns: op=00 a=3.140000 b=2500.000000 y=2503.140000

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