Cpu0p

Verilog 基本語法 型態 全域變數 基本元件 多樣的寫法 指定 assign always initial 運算式 分枝 迴圈 模組 函數 Task 陣列 輸出入 觀察 真值表 測試程式 訊息顯示 注意事項 模擬程序 硬體工程 程式範例 Xor Xor3 全加器 加法器 加減器 快速加法器 乘法器 ALU 閂鎖器 脈衝偵測 計數器 多工器 暫存器群 記憶體 延遲問題 浮點數 狀態機 程式計數器 CPU0-Mini CPU0 pipeline 工具 QuartusII Icarus Veritek 訊息 相關網站 參考文獻 最新修改 簡體版 English

文章 撰寫中：版本 cpu0p0.9.zip — 混雜 = 與 <= 的程式，但可以正確運作。 cpu0p1.0.zip — 只使用 = 的程式，可以正確運作。 cpu0p1.1.zip — 只使用 <= 的程式，無法正確運作，修改中。 規劃原則 指令與資料的存取必須使用兩組線路，因此有很多種可能的方法。 方案一：使用兩塊記憶體： iMem 與 dMem (哈佛架構) 方案二：使用一塊記憶體加兩個 cache：iCache 與 dCache 方案三：使用一塊記憶體，但是該記憶體有兩組位址線與資料線，也就是有 abus1, dbus1, abus2, dbus2 等兩組線。 本程式採用方案三單一記憶體兩組線的方式。 Verilog 程式：cpu0p.v // 管線狀態：IDLE 或 WAIT `define IDLE 2'b00 // 閒置中 `define WAIT_M 2'b01 // 等待回應 `define WAIT_ACK 2'b10 // 等待回應 // 寬度形態常數 `define INT32 2'b11 // 寬度 32 位元 `define INT24 2'b10 // 寬度 24 位元 `define INT16 2'b01 // 寬度 16 位元 `define BYTE 2'b00 // 寬度 8 位元 // 暫存器簡稱 `define PC cpu.R[15] // 程式計數器 `define LR cpu.R[14] // 連結暫存器 `define SP cpu.R[13] // 堆疊暫存器 `define SW cpu.R[12] // 狀態暫存器 `define IR cpu.ir // 指令暫存器 // 狀態暫存器旗標位元 `define N `SW[31] // 負號旗標 `define Z `SW[30] // 零旗標 `define C `SW[29] // 進位旗標 `define V `SW[28] // 溢位旗標 `define I `SW[7] // 硬體中斷許可 `define T `SW[6] // 軟體中斷許可 `define M `SW[0] // 模式位元 module iFetch(input clock, reset, iReady, output reg iGet, oReady, input oGet); reg [1:0] state; reg [31:0] pc, pc0; always @(posedge clock) begin if (reset) begin oReady=0; iGet=0; state=`IDLE; end else case (state) `IDLE: begin // 閒置中 #1; if (iReady) begin // 輸入資料已準備好 #1; memReadStart1(`PC, `INT32); pc0 = `PC; `PC = `PC+4; pc = `PC; iGet = 1; // 處理輸入資料 #1; state = `WAIT_ACK; // 進入等待狀態 oReady = 1; end end `WAIT_ACK:begin // 等待回應 (資料被取走) #1; if (oGet) begin // 資料被取走了 oReady = 0; // 下一筆輸出資料尚未準備好。 state = `IDLE; // 回到閒置狀態，準備取得下一筆輸入資料 end #1; iGet = 0; // 下一筆輸入資料尚未準備好。 end endcase end endmodule module iDecode(input clock, reset, iReady, output reg iGet, oReady, input oGet); parameter name="iDecode"; reg [1:0] state; reg [31:0] ir, pc, pc0; reg [7:0] op; reg [3:0] a, b, c; reg [4:0] c5; reg signed [11:0] cx12; reg signed [15:0] cx16; reg signed [23:0] cx24; reg signed [31:0] c12, c16, c24, Ra, Rb, Rc; // ipc:instruction PC always @(posedge clock) begin if (reset) begin oReady=0; iGet=0; state=`IDLE; end else case (state) `IDLE: begin // 閒置中 #1; if (iReady && (!cpu.m_en1 || cpu.m_ack1)) begin // 輸入資料已準備好 memReadEnd1(ir); // IR = dbus = m[PC] pc0 = cpu.if1.pc0; pc = cpu.if1.pc; $display("%-4d:fetch , pc0=%x pc=%x ir=%x", $stime, pc0, pc, ir); iGet = 1; // 處理輸入資料 {op, a, b, c, cx12} = ir; cx24 = ir[23:0]; cx16 = ir[15:0]; c5 = ir[4:0]; c12 = cx12; // 取出 cx12 並轉為 32 位元有號數 c12 c16 = cx16; // 取出 cx16 並轉為 32 位元有號數 c16 c24 = cx24; // 取出 cx24 並轉為 32 位元有號數 c24 Ra = cpu.R[a]; Rb = cpu.R[b]; Rc = cpu.R[c]; case (op) // 載入儲存指令 cpu.LD: memReadStart2(Rb+c16, `INT32); // 載入word; LD Ra, [Rb+Cx]; Ra<=[Rb+ Cx] cpu.ST: memWriteStart2(Rb+c16, Ra, `INT32); // 儲存word; ST Ra, [Rb+ Cx]; Ra=>[Rb+ Cx] cpu.LDB: memReadStart2(Rb+c16, `BYTE); // 載入byte; LDB Ra, [Rb+ Cx]; Ra<=(byte)[Rb+ Cx] cpu.STB: memWriteStart2(Rb+c16, Ra, `BYTE); // 儲存byte; STB Ra, [Rb+ Cx]; Ra=>(byte)[Rb+ Cx] cpu.LDR: memReadStart2(Rb+Rc, `INT32); // LD的Rc版; LDR Ra, [Rb+Rc]; Ra<=[Rb+ Rc] cpu.STR: memWriteStart2(Rb+Rc, Ra, `INT32); // ST的Rc版; STR Ra, [Rb+Rc]; Ra=>[Rb+ Rc] cpu.LBR: memReadStart2(Rb+Rc, `BYTE); // LDB的Rc版; LBR Ra, [Rb+Rc]; Ra<=(byte)[Rb+ Rc] cpu.SBR: memWriteStart2(Rb+Rc, Ra, `BYTE); // STB的Rc版; SBR Ra, [Rb+Rc]; Ra=>(byte)[Rb+ Rc] // 堆疊指令 cpu.PUSH:begin `SP = `SP-4; memWriteStart2(`SP, Ra, `INT32); end // 推入 word; PUSH Ra; SP-=4;[SP]<=Ra; cpu.POP: begin memReadStart2(`SP, `INT32); `SP = `SP + 4; end // 彈出 word; POP Ra; Ra=[SP];SP+=4; cpu.PUSHB:begin `SP = `SP-1; memWriteStart2(`SP, Ra, `BYTE); end // 推入 byte; PUSHB Ra; SP--;[SP]<=Ra;(byte) cpu.POPB:begin memReadStart2(`SP, `BYTE); `SP = `SP+1; end // 彈出 byte; POPB Ra; Ra<=[SP];SP++;(byte) endcase #1; oReady = 1; // 輸出資料已準備好 state = `WAIT_ACK; // 進入等待狀態 $display("%-4d:decode, pc0=%x pc=%x ir=%x op=%x a=%x b=%x c=%x cx12=%x", $stime, pc0, pc, ir, op, a, b, c, cx12); end #1; end `WAIT_ACK:begin // 等待回應 (資料被取走) #1; if (oGet) begin // 資料被取走了 oReady = 0; // 下一筆輸出資料尚未準備好。 state = `IDLE; // 回到閒置狀態，準備取得下一筆輸入資料 end #1; iGet = 0; // 下一筆輸入資料尚未準備好。 end endcase end endmodule module iExec(input clock, reset, iReady, output reg iGet, oReady, input oGet); parameter name="iExec"; reg [31:0] ir, pc, pc0; reg [7:0] op; reg [3:0] a, b, c; reg [4:0] c5; reg signed [31:0] c12, c16, c24, Ra, Rb, Rc; // ipc:instruction PC reg [1:0] state; reg [1:0] skip; always @(posedge clock) begin if (reset) begin oReady=0; iGet=0; state=`IDLE; skip = 0; end else case (state) `IDLE: begin // 閒置中 #1; if (iReady && (!cpu.m_en2 || cpu.m_ack2)) begin // 輸入資料已準備好 if (skip > 0) skip = skip-1; else begin // 處理輸入資料 pc0 = cpu.id1.pc0; pc = cpu.id1.pc; ir = cpu.id1.ir; op = cpu.id1.op; a = cpu.id1.a; b = cpu.id1.b; c = cpu.id1.c; c5 = cpu.id1.c5; c12 = cpu.id1.c12; c16 = cpu.id1.c16; c24 = cpu.id1.c24; Ra = cpu.id1.Ra; Rb = cpu.id1.Rb; Rc = cpu.id1.Rc; iGet = 1; // 準備輸出資料 case (op) cpu.LD, cpu.LDB, cpu.LDR, cpu.LBR, cpu.POP, cpu.POPB : memReadEnd2(cpu.R[a]); // 讀取記憶體完成 cpu.ST, cpu.STB, cpu.STR, cpu.SBR, cpu.PUSH, cpu.PUSHB: memWriteEnd2(); // 寫入記憶體完成 cpu.LDI: cpu.R[a] = Rb+c16; // 立即載入; LDI Ra, Rb+Cx; Ra<=Rb + Cx // 運算指令 cpu.CMP: begin `N=(Ra-Rb<0);`Z=(Ra-Rb==0); end // 比較; CMP Ra, Rb; SW=(Ra >=< Rb) cpu.MOV: regSet(a, Rb); // 移動; MOV Ra, Rb; Ra<=Rb cpu.ADD: regSet(a, Rb+Rc); // 加法; ADD Ra, Rb, Rc; Ra<=Rb+Rc cpu.SUB: regSet(a, Rb-Rc); // 減法; SUB Ra, Rb, Rc; Ra<=Rb-Rc cpu.MUL: regSet(a, Rb*Rc); // 乘法; MUL Ra, Rb, Rc; Ra<=Rb*Rc cpu.DIV: regSet(a, Rb/Rc); // 除法; DIV Ra, Rb, Rc; Ra<=Rb/Rc cpu.AND: regSet(a, Rb&Rc); // 位元 AND; AND Ra, Rb, Rc; Ra<=Rb and Rc cpu.OR: regSet(a, Rb|Rc); // 位元 OR; OR Ra, Rb, Rc; Ra<=Rb or Rc cpu.XOR: regSet(a, Rb^Rc); // 位元 XOR; XOR Ra, Rb, Rc; Ra<=Rb xor Rc cpu.SHL: regSet(a, Rb<<c5); // 向左移位; SHL Ra, Rb, Cx; Ra<=Rb << Cx cpu.SHR: regSet(a, Rb>>c5); // 向右移位; SHR Ra, Rb, Cx; Ra<=Rb >> Cx // 跳躍指令 cpu.JEQ: if (`Z) begin `PC=pc+c24; skip=2; end // 跳躍 (相等); JEQ Cx; if SW(=) PC PC+Cx cpu.JNE: if (!`Z) begin `PC=pc+c24; skip=2; end // 跳躍 (不相等); JNE Cx; if SW(!=) PC PC+Cx cpu.JLT: if (`N) begin `PC=pc+c24; skip=2; end // 跳躍 ( < ); JLT Cx; if SW(<) PC PC+Cx cpu.JGT: if (!`N&&!`Z) begin `PC=pc+c24; skip=2; end // 跳躍 ( > ); JGT Cx; if SW(>) PC PC+Cx cpu.JLE: if (`N || `Z) begin `PC=pc+c24; skip=2; end // 跳躍 ( <= ); JLE Cx; if SW(<=) PC PC+Cx cpu.JGE: if (!`N || `Z) begin `PC=pc+c24; skip=2; end // 跳躍 ( >= ); JGE Cx; if SW(>=) PC PC+Cx cpu.JMP: begin `PC = pc+c24; skip=2; end // 跳躍 (無條件); JMP Cx; PC <= PC+Cx cpu.SWI: begin `LR=pc;`PC= c24; `I = 1'b1; skip=2; end // 軟中斷; SWI Cx; LR <= PC; PC <= Cx; INT<=1 cpu.CALL:begin `LR=pc;`PC=pc + c24; skip=2; end // 跳到副程式; CALL Cx; LR<=PC; PC<=PC+Cx cpu.RET: begin `PC=`LR; skip=2; // 返回; RET; PC <= LR if (`PC < 0) begin $display("RET to PC < 0, finished!"); $finish; end end cpu.IRET:begin `PC=`LR;`I = 1'b0; skip=2; end // 中斷返回; IRET; PC <= LR; INT<=0 endcase Ra = cpu.R[a]; $display("%-4d:exec , pc0=%x ir=%x Ra=%x=%-4d Rb=%x Rc=%x", $stime, pc0, ir, Ra, Ra, Rb, Rc); end #1; oReady = 1; // 輸出資料已準備好 state = `WAIT_ACK; // 進入等待狀態 end end `WAIT_ACK:begin // 等待回應 (資料被取走) #1; if (oGet) begin // 資料被取走了 #1; oReady = 0; // 下一筆輸出資料尚未準備好。 state = `IDLE; // 回到閒置狀態，準備取得下一筆輸入資料 end #1; iGet = 0; // 下一筆輸入資料尚未準備好。 end endcase end endmodule module cpu(input clock, reset, output [31:0] ir, pc, output [31:0] mar1, mdr1, inout [31:0] dbus1, output reg m_en1, m_rw1, input m_ack1, output reg [1:0] m_size1, output [31:0] mar2, mdr2, inout [31:0] dbus2, output reg m_en2, m_rw2, input m_ack2, output reg [1:0] m_size2 ); // cpu0 是由 if1, id1, ie1, iw1 四根管子 (pipe) 連接後形成的管線 // 管線相關參數 wire ifiGet, idiGet, ieiGet, iwiGet; // pipe 輸入是否準備好了 wire ifoReady, idoReady, ieoReady, iwoReady; // pipe 輸出是否準備好了 parameter iReady = 1'b1, oGet=1'b1; // pipeline 的整體輸入輸出是否準備好了 (隨時都準備好，這樣才會不斷驅動)。 // 暫存器與欄位 reg [31:0] mar1, mdr1, mar2, mdr2; reg signed [31:0] R [0:15]; // 指令編碼表 parameter [7:0] LD=8'h00,ST=8'h01,LDB=8'h02,STB=8'h03,LDR=8'h04,STR=8'h05, LBR=8'h06,SBR=8'h07,LDI=8'h08,CMP=8'h10,MOV=8'h12,ADD=8'h13,SUB=8'h14, MUL=8'h15,DIV=8'h16,AND=8'h18,OR=8'h19,XOR=8'h1A,ROL=8'h1C,ROR=8'h1D, SHL=8'h1E,SHR=8'h1F,JEQ=8'h20,JNE=8'h21,JLT=8'h22,JGT=8'h23,JLE=8'h24, JGE=8'h25,JMP=8'h26,SWI=8'h2A,CALL=8'h2B,RET=8'h2C,IRET=8'h2D, PUSH=8'h30,POP=8'h31,PUSHB=8'h32,POPB=8'h33; task memReadStart1(input [31:0] addr, input [1:0] size); begin // 讀取記憶體 Word mar1 = addr; // read(m[addr]) m_rw1 = 1; // 讀取模式：read m_en1 = 1; // 啟動讀取 m_size1 = size; end endtask task memReadEnd1(output [31:0] data); begin // 讀取記憶體完成，取得資料 mdr1 = dbus1; // 取得記憶體傳回的 dbus = m[addr] data = dbus1; // 傳回資料 m_en1 = 0; // 讀取完畢 end endtask // 寫入記憶體 -- addr:寫入位址, data:寫入資料 task memWriteStart1(input [31:0] addr, input [31:0] data, input [1:0] size); begin mar1 = addr; // write(m[addr], data) mdr1 = data; m_rw1 = 0; // 寫入模式：write m_en1 = 1; // 啟動寫入 m_size1 = size; end endtask task memWriteEnd1; begin // 寫入記憶體完成 m_en1 = 0; // 寫入完畢 end endtask task memReadStart2(input [31:0] addr, input [1:0] size); begin // 讀取記憶體 Word mar2 = addr; // read(m[addr]) m_rw2 = 1; // 讀取模式：read m_en2 = 1; // 啟動讀取 m_size2 = size; end endtask task memReadEnd2(output [31:0] data); begin // 讀取記憶體完成，取得資料 mdr2 = dbus2; // 取得記憶體傳回的 dbus = m[addr] data = dbus2; // 傳回資料 m_en2 = 0; // 讀取完畢 end endtask // 寫入記憶體 -- addr:寫入位址, data:寫入資料 task memWriteStart2(input [31:0] addr, input [31:0] data, input [1:0] size); begin mar2 = addr; // write(m[addr], data) mdr2 = data; m_rw2 = 0; // 寫入模式：write m_en2 = 1; // 啟動寫入 m_size2 = size; end endtask task memWriteEnd2; begin // 寫入記憶體完成 m_en2 = 0; // 寫入完畢 end endtask task regSet(input [3:0] i, input [31:0] data); begin if (i!=0) R[i] = data; end endtask iFetch if1(clock, reset, iReady, ifiGet, ifoReady, idiGet); // 管子： iDecode id1(clock, reset, ifoReady, idiGet, idoReady, ieiGet); // 管子： iExec ie1(clock, reset, idoReady, ieiGet, ieoReady, oGet); // 管子： always @(posedge clock) begin if (reset) begin `PC = 0; R[0] = 0; `SW = 0; `LR = -1; end end endmodule module memory(input clock, reset, en1, en2, rw1, rw2, output reg ack1, ack2, input [1:0] size1, size2, input [31:0] abus1, abus2, dbus_in1, dbus_in2, output [31:0] dbus_out1, dbus_out2); reg [7:0] m [0:258]; reg [31:0] data1, data2; integer i; initial begin $readmemh("cpu0p.hex", m); for (i=0; i < 255; i=i+4) begin $display("%8x: %8x", i, {m[i], m[i+1], m[i+2], m[i+3]}); end end always @(*) begin if (en1) begin ack1 = 0; #30; if (abus1 >=0 && abus1 <= 255) begin if (rw1 == 0) begin // r_w==0:write data1 = dbus_in1; case (size1) `BYTE: {m[abus1]} = dbus_in1[7:0]; `INT16: {m[abus1], m[abus1+1] } = dbus_in1[15:0]; `INT24: {m[abus1], m[abus1+1], m[abus1+2]} = dbus_in1[24:0]; `INT32: {m[abus1], m[abus1+1], m[abus1+2], m[abus1+3]} = dbus_in1; endcase end else begin// rw == 1:read case (size1) `BYTE: data1 = {8'h00 , 8'h00, 8'h00, m[abus1] }; `INT16: data1 = {8'h00 , 8'h00, m[abus1], m[abus1+1] }; `INT24: data1 = {8'h00 , m[abus1], m[abus1+1], m[abus1+2] }; `INT32: data1 = {m[abus1], m[abus1+1], m[abus1+2], m[abus1+3]}; endcase end end ack1 = 1; end else begin data1 = 32'hZZZZZZZZ; ack1 = 0; end end assign dbus_out1 = data1; always @(*) begin if (en2) begin ack2 = 0; #30; if (abus2 >=0 && abus2 <= 255) begin if (rw2 == 0) begin // r_w==0:write data2 = dbus_in2; case (size2) `BYTE: {m[abus2]} = dbus_in2[7:0]; `INT16: {m[abus2], m[abus2+1] } = dbus_in2[15:0]; `INT24: {m[abus2], m[abus2+1], m[abus2+2]} = dbus_in2[24:0]; `INT32: {m[abus2], m[abus2+1], m[abus2+2], m[abus2+3]} = dbus_in2; endcase end else begin// rw == 1:read case (size2) `BYTE: data2 = {8'h00 , 8'h00, 8'h00, m[abus2] }; `INT16: data2 = {8'h00 , 8'h00, m[abus2], m[abus2+1] }; `INT24: data2 = {8'h00 , m[abus2], m[abus2+1], m[abus2+2] }; `INT32: data2 = {m[abus2], m[abus2+1], m[abus2+2], m[abus2+3]}; endcase end end ack2 = 1; end else begin data2 = 32'hZZZZZZZZ; ack2 = 0; end end assign dbus_out2 = data2; endmodule module main; reg clock, reset; wire [31:0] pc, ir; wire [31:0] mar1, mar2, mdr1, mdr2, dbus1, dbus2; wire m_en1, m_en2, m_rw1, m_rw2, m_ack1, m_ack2; wire [1:0] m_size1, m_size2; cpu cpu0(.clock(clock), .reset(reset), .pc(pc), .ir(ir), .mar1(mar1), .mdr1(mdr1), .dbus1(dbus1), .m_en1(m_en1), .m_rw1(m_rw1), .m_size1(m_size1), .m_ack1(m_ack1), .mar2(mar2), .mdr2(mdr2), .dbus2(dbus2), .m_en2(m_en2), .m_rw2(m_rw2), .m_size2(m_size2), .m_ack2(m_ack2)); memory memory0(.clock(clock), .reset(reset), .en1(m_en1), .rw1(m_rw1), .ack1(m_ack1), .size1(m_size1), .abus1(mar1), .dbus_in1(mdr1), .dbus_out1(dbus1), .en2(m_en2), .rw2(m_rw2), .ack2(m_ack2), .size2(m_size2), .abus2(mar2), .dbus_in2(mdr2), .dbus_out2(dbus2)); initial begin clock = 0; reset = 1; #50 reset = 0; #10000 $finish; end always #10 clock=clock+1; endmodule Icarus 模擬結果 D:\oc\cpu0p>vvp cpu0p WARNING: cpu0p.v:312: $readmemh(cpu0p.hex): Not enough words in the file for the requested range [0:258]. 00000000: 00df00b6 00000004: 08400004 00000008: 08500008 0000000c: 054d5000 00000010: 046d5000 00000014: 075d4000 00000018: 066d4000 0000001c: 30e00000 00000020: 12850000 00000024: 13854000 00000028: 14854000 0000002c: 15854000 00000030: 16854000 00000034: 18854000 00000038: 19854000 0000003c: 1a854000 00000040: 1e850003 00000044: 1f850002 00000048: 10450000 0000004c: 20000018 00000050: 23000014 00000054: 25000010 00000058: 2200000c 0000005c: 24000008 00000060: 21000004 00000064: 26000000 00000068: 0810000a 0000006c: 2b000008 00000070: 31e00000 00000074: 2c000000 00000078: 30e00000 0000007c: 12300000 00000080: 024f0024 00000084: 08200000 00000088: 13223000 0000008c: 13334000 00000090: 10310000 00000094: 24fffff0 00000098: 012f000d 0000009c: 033f000d 000000a0: 31e00000 000000a4: 2c000000 000000a8: 01000000 000000ac: 00000001 000000b0: 02030405 000000b4: 06070809 000000b8: 0a0b0000 000000bc: 00ba0102 000000c0: 03040506 000000c4: 0708xxxx 000000c8: xxxxxxxx 000000cc: xxxxxxxx 000000d0: xxxxxxxx 000000d4: xxxxxxxx 000000d8: xxxxxxxx 000000dc: xxxxxxxx 000000e0: xxxxxxxx 000000e4: xxxxxxxx 000000e8: xxxxxxxx 000000ec: xxxxxxxx 000000f0: xxxxxxxx 000000f4: xxxxxxxx 000000f8: xxxxxxxx 000000fc: xxxxxxxx 91 :fetch , pc0=00000000 pc=00000004 ir=00df00b6 92 :decode, pc0=00000000 pc=00000004 ir=00df00b6 op=00 a=d b=f c=0 cx12=0b6 131 :exec , pc0=00000000 ir=00df00b6 Ra=000000ba=186 Rb=00000004 Rc=00000000 171 :fetch , pc0=00000004 pc=00000008 ir=08400004 172 :decode, pc0=00000004 pc=00000008 ir=08400004 op=08 a=4 b=0 c=0 cx12=004 191 :exec , pc0=00000004 ir=08400004 Ra=00000004=4 Rb=00000000 Rc=00000000 251 :fetch , pc0=00000008 pc=0000000c ir=08500008 252 :decode, pc0=00000008 pc=0000000c ir=08500008 op=08 a=5 b=0 c=0 cx12=008 271 :exec , pc0=00000008 ir=08500008 Ra=00000008=8 Rb=00000000 Rc=00000000 311 :fetch , pc0=0000000c pc=00000010 ir=054d5000 312 :decode, pc0=0000000c pc=00000010 ir=054d5000 op=05 a=4 b=d c=5 cx12=000 351 :exec , pc0=0000000c ir=054d5000 Ra=00000004=4 Rb=000000ba Rc=00000008 391 :fetch , pc0=00000010 pc=00000014 ir=046d5000 392 :decode, pc0=00000010 pc=00000014 ir=046d5000 op=04 a=6 b=d c=5 cx12=000 431 :exec , pc0=00000010 ir=046d5000 Ra=00000004=4 Rb=000000ba Rc=00000008 471 :fetch , pc0=00000014 pc=00000018 ir=075d4000 472 :decode, pc0=00000014 pc=00000018 ir=075d4000 op=07 a=5 b=d c=4 cx12=000 511 :exec , pc0=00000014 ir=075d4000 Ra=00000008=8 Rb=000000ba Rc=00000004 551 :fetch , pc0=00000018 pc=0000001c ir=066d4000 552 :decode, pc0=00000018 pc=0000001c ir=066d4000 op=06 a=6 b=d c=4 cx12=000 591 :exec , pc0=00000018 ir=066d4000 Ra=00000008=8 Rb=000000ba Rc=00000004 631 :fetch , pc0=0000001c pc=00000020 ir=30e00000 632 :decode, pc0=0000001c pc=00000020 ir=30e00000 op=30 a=e b=0 c=0 cx12=000 671 :exec , pc0=0000001c ir=30e00000 Ra=ffffffff=-1 Rb=00000000 Rc=00000000 711 :fetch , pc0=00000020 pc=00000024 ir=12850000 712 :decode, pc0=00000020 pc=00000024 ir=12850000 op=12 a=8 b=5 c=0 cx12=000 731 :exec , pc0=00000020 ir=12850000 Ra=00000008=8 Rb=00000008 Rc=00000000 791 :fetch , pc0=00000024 pc=00000028 ir=13854000 792 :decode, pc0=00000024 pc=00000028 ir=13854000 op=13 a=8 b=5 c=4 cx12=000 811 :exec , pc0=00000024 ir=13854000 Ra=0000000c=12 Rb=00000008 Rc=00000004 851 :fetch , pc0=00000028 pc=0000002c ir=14854000 852 :decode, pc0=00000028 pc=0000002c ir=14854000 op=14 a=8 b=5 c=4 cx12=000 871 :exec , pc0=00000028 ir=14854000 Ra=00000004=4 Rb=00000008 Rc=00000004 911 :fetch , pc0=0000002c pc=00000030 ir=15854000 912 :decode, pc0=0000002c pc=00000030 ir=15854000 op=15 a=8 b=5 c=4 cx12=000 931 :exec , pc0=0000002c ir=15854000 Ra=00000020=32 Rb=00000008 Rc=00000004 971 :fetch , pc0=00000030 pc=00000034 ir=16854000 972 :decode, pc0=00000030 pc=00000034 ir=16854000 op=16 a=8 b=5 c=4 cx12=000 991 :exec , pc0=00000030 ir=16854000 Ra=00000002=2 Rb=00000008 Rc=00000004 1031:fetch , pc0=00000034 pc=00000038 ir=18854000 1032:decode, pc0=00000034 pc=00000038 ir=18854000 op=18 a=8 b=5 c=4 cx12=000 1051:exec , pc0=00000034 ir=18854000 Ra=00000000=0 Rb=00000008 Rc=00000004 1091:fetch , pc0=00000038 pc=0000003c ir=19854000 1092:decode, pc0=00000038 pc=0000003c ir=19854000 op=19 a=8 b=5 c=4 cx12=000 1111:exec , pc0=00000038 ir=19854000 Ra=0000000c=12 Rb=00000008 Rc=00000004 1151:fetch , pc0=0000003c pc=00000040 ir=1a854000 1152:decode, pc0=0000003c pc=00000040 ir=1a854000 op=1a a=8 b=5 c=4 cx12=000 1171:exec , pc0=0000003c ir=1a854000 Ra=0000000c=12 Rb=00000008 Rc=00000004 1211:fetch , pc0=00000040 pc=00000044 ir=1e850003 1212:decode, pc0=00000040 pc=00000044 ir=1e850003 op=1e a=8 b=5 c=0 cx12=003 1231:exec , pc0=00000040 ir=1e850003 Ra=00000040=64 Rb=00000008 Rc=00000000 1271:fetch , pc0=00000044 pc=00000048 ir=1f850002 1272:decode, pc0=00000044 pc=00000048 ir=1f850002 op=1f a=8 b=5 c=0 cx12=002 1291:exec , pc0=00000044 ir=1f850002 Ra=00000002=2 Rb=00000008 Rc=00000000 1331:fetch , pc0=00000048 pc=0000004c ir=10450000 1332:decode, pc0=00000048 pc=0000004c ir=10450000 op=10 a=4 b=5 c=0 cx12=000 1351:exec , pc0=00000048 ir=10450000 Ra=00000004=4 Rb=00000008 Rc=00000000 1391:fetch , pc0=0000004c pc=00000050 ir=20000018 1392:decode, pc0=0000004c pc=00000050 ir=20000018 op=20 a=0 b=0 c=0 cx12=018 1411:exec , pc0=0000004c ir=20000018 Ra=00000000=0 Rb=00000000 Rc=00000000 1451:fetch , pc0=00000050 pc=00000054 ir=23000014 1452:decode, pc0=00000050 pc=00000054 ir=23000014 op=23 a=0 b=0 c=0 cx12=014 1471:exec , pc0=00000050 ir=23000014 Ra=00000000=0 Rb=00000000 Rc=00000000 1511:fetch , pc0=00000054 pc=00000058 ir=25000010 1512:decode, pc0=00000054 pc=00000058 ir=25000010 op=25 a=0 b=0 c=0 cx12=010 1531:exec , pc0=00000054 ir=25000010 Ra=00000000=0 Rb=00000000 Rc=00000000 1571:fetch , pc0=00000058 pc=0000005c ir=2200000c 1572:decode, pc0=00000058 pc=0000005c ir=2200000c op=22 a=0 b=0 c=0 cx12=00c 1591:exec , pc0=00000058 ir=2200000c Ra=00000000=0 Rb=00000000 Rc=00000000 1631:fetch , pc0=00000068 pc=0000006c ir=0810000a 1632:decode, pc0=00000068 pc=0000006c ir=0810000a op=08 a=1 b=0 c=0 cx12=00a 1731:exec , pc0=00000068 ir=0810000a Ra=0000000a=10 Rb=00000000 Rc=00000000 1751:fetch , pc0=0000006c pc=00000070 ir=2b000008 1752:decode, pc0=0000006c pc=00000070 ir=2b000008 op=2b a=0 b=0 c=0 cx12=008 1771:exec , pc0=0000006c ir=2b000008 Ra=00000000=0 Rb=00000000 Rc=00000000 1831:fetch , pc0=00000078 pc=0000007c ir=30e00000 1832:decode, pc0=00000078 pc=0000007c ir=30e00000 op=30 a=e b=0 c=0 cx12=000 1951:exec , pc0=00000078 ir=30e00000 Ra=00000070=112 Rb=00000000 Rc=00000000 1971:fetch , pc0=0000007c pc=00000080 ir=12300000 1972:decode, pc0=0000007c pc=00000080 ir=12300000 op=12 a=3 b=0 c=0 cx12=000 1991:exec , pc0=0000007c ir=12300000 Ra=00000000=0 Rb=00000000 Rc=00000000 2031:fetch , pc0=00000080 pc=00000084 ir=024f0024 2032:decode, pc0=00000080 pc=00000084 ir=024f0024 op=02 a=4 b=f c=0 cx12=024 2071:exec , pc0=00000080 ir=024f0024 Ra=00000001=1 Rb=00000084 Rc=00000000 2111:fetch , pc0=00000084 pc=00000088 ir=08200000 2112:decode, pc0=00000084 pc=00000088 ir=08200000 op=08 a=2 b=0 c=0 cx12=000 2131:exec , pc0=00000084 ir=08200000 Ra=00000000=0 Rb=00000000 Rc=00000000 2191:fetch , pc0=00000088 pc=0000008c ir=13223000 2192:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 2211:exec , pc0=00000088 ir=13223000 Ra=00000000=0 Rb=00000000 Rc=00000000 2251:fetch , pc0=0000008c pc=00000090 ir=13334000 2252:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 2271:exec , pc0=0000008c ir=13334000 Ra=00000001=1 Rb=00000000 Rc=00000001 2311:fetch , pc0=00000090 pc=00000094 ir=10310000 2312:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 2331:exec , pc0=00000090 ir=10310000 Ra=00000001=1 Rb=0000000a Rc=00000000 2371:fetch , pc0=00000094 pc=00000098 ir=24fffff0 2372:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 2391:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 2431:fetch , pc0=00000088 pc=0000008c ir=13223000 2432:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 2531:exec , pc0=00000088 ir=13223000 Ra=00000001=1 Rb=00000000 Rc=00000001 2551:fetch , pc0=0000008c pc=00000090 ir=13334000 2552:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 2571:exec , pc0=0000008c ir=13334000 Ra=00000002=2 Rb=00000001 Rc=00000001 2631:fetch , pc0=00000090 pc=00000094 ir=10310000 2632:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 2651:exec , pc0=00000090 ir=10310000 Ra=00000002=2 Rb=0000000a Rc=00000000 2691:fetch , pc0=00000094 pc=00000098 ir=24fffff0 2692:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 2711:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 2751:fetch , pc0=00000088 pc=0000008c ir=13223000 2752:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 2851:exec , pc0=00000088 ir=13223000 Ra=00000003=3 Rb=00000001 Rc=00000002 2871:fetch , pc0=0000008c pc=00000090 ir=13334000 2872:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 2891:exec , pc0=0000008c ir=13334000 Ra=00000003=3 Rb=00000002 Rc=00000001 2951:fetch , pc0=00000090 pc=00000094 ir=10310000 2952:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 2971:exec , pc0=00000090 ir=10310000 Ra=00000003=3 Rb=0000000a Rc=00000000 3011:fetch , pc0=00000094 pc=00000098 ir=24fffff0 3012:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 3031:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 3071:fetch , pc0=00000088 pc=0000008c ir=13223000 3072:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 3171:exec , pc0=00000088 ir=13223000 Ra=00000006=6 Rb=00000003 Rc=00000003 3191:fetch , pc0=0000008c pc=00000090 ir=13334000 3192:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 3211:exec , pc0=0000008c ir=13334000 Ra=00000004=4 Rb=00000003 Rc=00000001 3271:fetch , pc0=00000090 pc=00000094 ir=10310000 3272:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 3291:exec , pc0=00000090 ir=10310000 Ra=00000004=4 Rb=0000000a Rc=00000000 3331:fetch , pc0=00000094 pc=00000098 ir=24fffff0 3332:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 3351:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 3391:fetch , pc0=00000088 pc=0000008c ir=13223000 3392:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 3491:exec , pc0=00000088 ir=13223000 Ra=0000000a=10 Rb=00000006 Rc=00000004 3511:fetch , pc0=0000008c pc=00000090 ir=13334000 3512:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 3531:exec , pc0=0000008c ir=13334000 Ra=00000005=5 Rb=00000004 Rc=00000001 3591:fetch , pc0=00000090 pc=00000094 ir=10310000 3592:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 3611:exec , pc0=00000090 ir=10310000 Ra=00000005=5 Rb=0000000a Rc=00000000 3651:fetch , pc0=00000094 pc=00000098 ir=24fffff0 3652:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 3671:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 3711:fetch , pc0=00000088 pc=0000008c ir=13223000 3712:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 3811:exec , pc0=00000088 ir=13223000 Ra=0000000f=15 Rb=0000000a Rc=00000005 3831:fetch , pc0=0000008c pc=00000090 ir=13334000 3832:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 3851:exec , pc0=0000008c ir=13334000 Ra=00000006=6 Rb=00000005 Rc=00000001 3911:fetch , pc0=00000090 pc=00000094 ir=10310000 3912:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 3931:exec , pc0=00000090 ir=10310000 Ra=00000006=6 Rb=0000000a Rc=00000000 3971:fetch , pc0=00000094 pc=00000098 ir=24fffff0 3972:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 3991:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 4031:fetch , pc0=00000088 pc=0000008c ir=13223000 4032:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 4131:exec , pc0=00000088 ir=13223000 Ra=00000015=21 Rb=0000000f Rc=00000006 4151:fetch , pc0=0000008c pc=00000090 ir=13334000 4152:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 4171:exec , pc0=0000008c ir=13334000 Ra=00000007=7 Rb=00000006 Rc=00000001 4231:fetch , pc0=00000090 pc=00000094 ir=10310000 4232:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 4251:exec , pc0=00000090 ir=10310000 Ra=00000007=7 Rb=0000000a Rc=00000000 4291:fetch , pc0=00000094 pc=00000098 ir=24fffff0 4292:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 4311:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 4351:fetch , pc0=00000088 pc=0000008c ir=13223000 4352:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 4451:exec , pc0=00000088 ir=13223000 Ra=0000001c=28 Rb=00000015 Rc=00000007 4471:fetch , pc0=0000008c pc=00000090 ir=13334000 4472:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 4491:exec , pc0=0000008c ir=13334000 Ra=00000008=8 Rb=00000007 Rc=00000001 4551:fetch , pc0=00000090 pc=00000094 ir=10310000 4552:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 4571:exec , pc0=00000090 ir=10310000 Ra=00000008=8 Rb=0000000a Rc=00000000 4611:fetch , pc0=00000094 pc=00000098 ir=24fffff0 4612:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 4631:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 4671:fetch , pc0=00000088 pc=0000008c ir=13223000 4672:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 4771:exec , pc0=00000088 ir=13223000 Ra=00000024=36 Rb=0000001c Rc=00000008 4791:fetch , pc0=0000008c pc=00000090 ir=13334000 4792:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 4811:exec , pc0=0000008c ir=13334000 Ra=00000009=9 Rb=00000008 Rc=00000001 4871:fetch , pc0=00000090 pc=00000094 ir=10310000 4872:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 4891:exec , pc0=00000090 ir=10310000 Ra=00000009=9 Rb=0000000a Rc=00000000 4931:fetch , pc0=00000094 pc=00000098 ir=24fffff0 4932:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 4951:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 4991:fetch , pc0=00000088 pc=0000008c ir=13223000 4992:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 5091:exec , pc0=00000088 ir=13223000 Ra=0000002d=45 Rb=00000024 Rc=00000009 5111:fetch , pc0=0000008c pc=00000090 ir=13334000 5112:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 5131:exec , pc0=0000008c ir=13334000 Ra=0000000a=10 Rb=00000009 Rc=00000001 5191:fetch , pc0=00000090 pc=00000094 ir=10310000 5192:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 5211:exec , pc0=00000090 ir=10310000 Ra=0000000a=10 Rb=0000000a Rc=00000000 5251:fetch , pc0=00000094 pc=00000098 ir=24fffff0 5252:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 5271:exec , pc0=00000094 ir=24fffff0 Ra=00000088=136 Rb=00000098 Rc=00000098 5311:fetch , pc0=00000088 pc=0000008c ir=13223000 5312:decode, pc0=00000088 pc=0000008c ir=13223000 op=13 a=2 b=2 c=3 cx12=000 5411:exec , pc0=00000088 ir=13223000 Ra=00000037=55 Rb=0000002d Rc=0000000a 5431:fetch , pc0=0000008c pc=00000090 ir=13334000 5432:decode, pc0=0000008c pc=00000090 ir=13334000 op=13 a=3 b=3 c=4 cx12=000 5451:exec , pc0=0000008c ir=13334000 Ra=0000000b=11 Rb=0000000a Rc=00000001 5511:fetch , pc0=00000090 pc=00000094 ir=10310000 5512:decode, pc0=00000090 pc=00000094 ir=10310000 op=10 a=3 b=1 c=0 cx12=000 5531:exec , pc0=00000090 ir=10310000 Ra=0000000b=11 Rb=0000000a Rc=00000000 5571:fetch , pc0=00000094 pc=00000098 ir=24fffff0 5572:decode, pc0=00000094 pc=00000098 ir=24fffff0 op=24 a=f b=f c=f cx12=ff0 5591:exec , pc0=00000094 ir=24fffff0 Ra=00000098=152 Rb=00000098 Rc=00000098 5631:fetch , pc0=00000098 pc=0000009c ir=012f000d 5632:decode, pc0=00000098 pc=0000009c ir=012f000d op=01 a=2 b=f c=0 cx12=00d 5671:exec , pc0=00000098 ir=012f000d Ra=00000037=55 Rb=0000009c Rc=00000000 5711:fetch , pc0=0000009c pc=000000a0 ir=033f000d 5712:decode, pc0=0000009c pc=000000a0 ir=033f000d op=03 a=3 b=f c=0 cx12=00d 5751:exec , pc0=0000009c ir=033f000d Ra=0000000b=11 Rb=000000a0 Rc=00000000 5791:fetch , pc0=000000a0 pc=000000a4 ir=31e00000 5792:decode, pc0=000000a0 pc=000000a4 ir=31e00000 op=31 a=e b=0 c=0 cx12=000 5831:exec , pc0=000000a0 ir=31e00000 Ra=00000070=112 Rb=00000000 Rc=00000000 5871:fetch , pc0=000000a4 pc=000000a8 ir=2c000000 5872:decode, pc0=000000a4 pc=000000a8 ir=2c000000 op=2c a=0 b=0 c=0 cx12=000 5891:exec , pc0=000000a4 ir=2c000000 Ra=00000000=0 Rb=00000000 Rc=00000000 5951:fetch , pc0=00000070 pc=00000074 ir=31e00000 5952:decode, pc0=00000070 pc=00000074 ir=31e00000 op=31 a=e b=0 c=0 cx12=000 6071:exec , pc0=00000070 ir=31e00000 Ra=ffffffff=-1 Rb=00000000 Rc=00000000 6091:fetch , pc0=00000074 pc=00000078 ir=2c000000 6092:decode, pc0=00000074 pc=00000078 ir=2c000000 op=2c a=0 b=0 c=0 cx12=000 RET to PC < 0, finished! Facebook 留言 Facebook Wikidot Post preview: Close preview or Sign in as Wikidot user (will not be published) - + Help: wiki text quick reference 授權 本網頁的作者、授權與引用方式 作者 陳鍾誠，於金門大學資訊工程系，電子郵件：wt.ude.uqn|ccc#wt.ude.uqn|ccc，網站：http://ccckmit.wikidot.com。 授權 本文採用創作共用 (Creative Common) 3.0 版的 姓名標示─非商業性─相同方式分享 授權條款，歡迎轉載或修改使用，但若做為商業使用時必須取得授權，引用本文時請參考下列格式。 中文版 (APA格式) 陳鍾誠 (13 Jun 2012 03:34)，(網頁標題) Cpu0p，(網站標題) 陳鍾誠的網站，取自 http://ccckmit.wikidot.com/ve:cpu0p ，網頁修改第 33 版。 英文版 (APA格式) Chung-Chen Chen (13 Jun 2012 03:34), Retrieved from http://ccckmit.wikidot.com/ve:cpu0p , Page Revision 33.