module counter(input clk, rst, output reg [2:0] q);
    always @(posedge clk) begin
        if (rst)
            q = 3'b000;
        else
            q = q+1;
    end
endmodule

Verilog 測試程式

`timescale 1ns/10ps

module counterTest;
reg clk;
reg rst;
wire [2:0] q;

counter DUT (.clk(clk), .rst(rst), .q(q));

initial
begin
  clk = 0;
  rst = 1;
end

initial #100 rst = 0;

always #50 clk=clk+1;

endmodule

執行結果

程式：針對 Icarus 修改的

檔案：counter.v

module counter(input clk, rst, output reg [2:0] q);
    always @(posedge clk) begin
        if (rst)
            q = 3'b000;
        else
            q = q+1;
    end
endmodule

module counterTest;
reg clk;
reg rst;
wire [2:0] q;

counter DUT (.clk(clk), .rst(rst), .q(q));

initial
begin
  clk = 0;
  rst = 1;
end

initial #100 rst = 0;

always #50 clk=clk+1;

always @(negedge clk) begin
   $display("q=%d", q);
end

initial #2000 $finish;

endmodule

Icarus 執行結果

D:\ccc101\icarus\ccc>iverilog -o count count.v

D:\ccc101\icarus\ccc>vvp count
q=0
q=1
q=2
q=3
q=4
q=5
q=6
q=7
q=0
q=1
q=2
q=3
q=4
q=5
q=6
q=7
q=0
q=1
q=2
q=3