指定 -- 平行與循序

Verilog

基本語法

型態

全域變數

基本元件

多樣的寫法

指定

assign

always

initial

運算式

分枝

迴圈

模組

函數

Task

陣列

輸出入

觀察

真值表

測試程式

訊息顯示

注意事項

模擬程序

硬體工程

程式範例

Xor

Xor3

全加器

加法器

加減器

快速加法器

乘法器

ALU

閂鎖器

脈衝偵測

計數器

多工器

暫存器群

記憶體

延遲問題

浮點數

狀態機

程式計數器

CPU0-Mini

CPU0

pipeline

工具

QuartusII

Icarus

Veritek

訊息

相關網站

參考文獻

最新修改

簡體版

English

結論

  • Combinational Logic :
    • No delays : Use blocking assignment (a=b; )
    • Inertial delay : Use delay evaluation blocking assignments (#5 a=b;)
    • Transport delays : Use delayed assignment non-blocking assignments (a <= #5 b; )
  1. Sequential Logic :
    • No delays : Use non-blockig assignments (q<=d)
    • With delays : Use delayed assignment non-blocking assignments (q<= #5 d;)

範例:DelayedEval.v

module main;
reg [7:0] A, B;
initial begin
    #5 A=1;
    #5 A=A+1;
    B=A+1;
    $display("A=%d B=%d", A, B);
end
endmodule

執行結果

D:\oc\assignment>iverilog delayedEval.v -o delayedEval

D:\oc\assignment>vvp delayedEval
A=  2 B=  3

參考文獻

  1. Understanding Verilog Blocking and Nonblocking Assignment (超經典,一定要看!)

摘錄:

Time 0:
➤ Q1 — (in any order) :
➤ Evaluate RHS of  all non-blocking assignments
➤ Evaluate RHS and change LHS of  all blocking assignments
➤ Evaluate RHS and change LHS of all continuous assignments
➤ Evaluate inputs and change outputs of all primitives
➤ Evaluate and print output from $display and $write
➤ Q2 — (in any order)  :
➤ Change LHS of all non-blocking assignments
➤ Q3 — (in any order) :
➤ Evaluate and print output from $monitor and $strobe
➤ Call PLI with reason_synchronize
➤ Q4 :
➤ Call PLI with reason_rosynchronize

...

Rules of Thumb for Procedural Assignments

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