# 結論

• Combinational Logic :
• No delays : Use blocking assignment (a=b; )
• Inertial delay : Use delay evaluation blocking assignments (#5 a=b;)
• Transport delays : Use delayed assignment non-blocking assignments (a <= #5 b; )
1. Sequential Logic :
• No delays : Use non-blockig assignments (q<=d)
• With delays : Use delayed assignment non-blocking assignments (q<= #5 d;)

# 範例：DelayedEval.v

``````module main;
reg [7:0] A, B;
initial begin
#5 A=1;
#5 A=A+1;
B=A+1;
\$display("A=%d B=%d", A, B);
end
endmodule```
```

``````D:\oc\assignment>iverilog delayedEval.v -o delayedEval

D:\oc\assignment>vvp delayedEval
A=  2 B=  3```
```

# 參考文獻

1. Understanding Verilog Blocking and Nonblocking Assignment (超經典，一定要看！)

``````Time 0:
➤ Q1 — (in any order) :
➤ Evaluate RHS of  all non-blocking assignments
➤ Evaluate RHS and change LHS of  all blocking assignments
➤ Evaluate RHS and change LHS of all continuous assignments
➤ Evaluate inputs and change outputs of all primitives
➤ Evaluate and print output from \$display and \$write
➤ Q2 — (in any order)  :
➤ Change LHS of all non-blocking assignments
➤ Q3 — (in any order) :
➤ Evaluate and print output from \$monitor and \$strobe
➤ Call PLI with reason_synchronize
➤ Q4 :
➤ Call PLI with reason_rosynchronize

...

Rules of Thumb for Procedural Assignments```
```