assign 與 always 之不同

``````module Seg7(input [3:0] num, output [7:0] seg);
reg [7:0] tseg;
always @(num) begin
case (num)
4'b0000: tseg = 8'b11111100; // 0
4'b0001: tseg = 8'b01100000; // 1
4'b0010: tseg = 8'b01011010; // 2
4'b0011: tseg = 8'b11110010; // 3
4'b0100: tseg = 8'b01100110; // 4
4'b0101: tseg = 8'b10110110; // 5
4'b0110: tseg = 8'b10111110; // 6
4'b0111: tseg = 8'b11100100; // 7
4'b1000: tseg = 8'b11111110; // 8
4'b1001: tseg = 8'b11110110; // 9
default: tseg = 8'b00000000; //
endcase
// seg = tseg;
end
assign seg = tseg;
endmodule```
```

指定的方法

兩種 Assign ：Blocking v.s. Nonblocking

a = b ; // Blocking assignment : 執行順序不一定，

a <= b; // Nonblocking assignment : 所有可同時值行的東西都要執行完一次後，才會前進到下一個時間點。

指定的範例

``````wire [8:0] sum;
wire [7:0] a, b;
wire carryin;

assign sum = a + b + carryin; // 當 a, b, carryin 有任何一個改變時，此語句都會被重新觸發。```
```

(除非是 primitives 或 continuous assignment 兩者的左邊才能是 wire 型態)。

Block 與 Nonblocking 的比較範例

比較一：

``````reg d1, d2, d3, d4;

always @(posedge clk) d2 = d1;
always @(posedge clk) d3 = d2;
always @(posedge clk) d4 = d3;```
```

``````reg d1, d2, d3, d4;

always @(posedge clk) d2 <= d1;
always @(posedge clk) d3 <= d2;
always @(posedge clk) d4 <= d3;```
```

比較二：

Blocking Assignment: 執行結果相當於 a=1, b=1, c=1

``````a = 1;
b = a;
c = b;```
```

NonBlocking Assignment: 執行結果相當於 a=1; b = 上一輪的 a; c=上一輪的 b;

``````a <= 1;
b <= a;
c <= b;```
```

參考文獻

1. Understanding Verilog Blocking and Nonblocking Assignments (讚！推薦！)
2. (筆記) 如何使用blocking與nonblocking assignment? (SOC) (Verilog)