4 位元加法器

Verilog 基本語法 型態 全域變數 基本元件 多樣的寫法 指定 assign always initial 運算式 分枝 迴圈 模組 函數 Task 陣列 輸出入 觀察 真值表 測試程式 訊息顯示 注意事項 模擬程序 硬體工程 程式範例 Xor Xor3 全加器 加法器 加減器 快速加法器 乘法器 ALU 閂鎖器 脈衝偵測 計數器 多工器 暫存器群 記憶體 延遲問題 浮點數 狀態機 程式計數器 CPU0-Mini CPU0 pipeline 工具 QuartusII Icarus Veritek 訊息 相關網站 參考文獻 最新修改 簡體版 English

文章 有號數的加法 程式：sadd4.v module fulladder (input a, b, c_in, output sum, c_out); wire s1, c1, c2; xor g1(s1, a, b); xor g2(sum, s1, c_in); and g3(c1, a,b); and g4(c2, s1, c_in) ; xor g5(c_out, c2, c1) ; endmodule module adder4(input signed [3:0] a, input signed [3:0] b, input c_in, output signed [3:0] sum, output c_out); wire [3:0] c; fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ; fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ; fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ; fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ; endmodule module main; reg signed [3:0] a; reg signed [3:0] b; wire signed [3:0] sum; wire c_out; adder4 DUT (a, b, 1'b0, sum, c_out); initial begin a = 4'b0101; b = 4'b0000; end always #50 begin b=b+1; $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum); end initial #2000 $finish; endmodule Icarus 編譯執行 D:\ccc101\icarus\ccc>iverilog -o sadd4 sadd4.v D:\ccc101\icarus\ccc>vvp sadd4 50ns monitor: a= 5 b= 1 sum= 6 100ns monitor: a= 5 b= 2 sum= 7 150ns monitor: a= 5 b= 3 sum=-8 200ns monitor: a= 5 b= 4 sum=-7 250ns monitor: a= 5 b= 5 sum=-6 300ns monitor: a= 5 b= 6 sum=-5 350ns monitor: a= 5 b= 7 sum=-4 400ns monitor: a= 5 b=-8 sum=-3 450ns monitor: a= 5 b=-7 sum=-2 500ns monitor: a= 5 b=-6 sum=-1 550ns monitor: a= 5 b=-5 sum= 0 600ns monitor: a= 5 b=-4 sum= 1 650ns monitor: a= 5 b=-3 sum= 2 700ns monitor: a= 5 b=-2 sum= 3 750ns monitor: a= 5 b=-1 sum= 4 800ns monitor: a= 5 b= 0 sum= 5 850ns monitor: a= 5 b= 1 sum= 6 900ns monitor: a= 5 b= 2 sum= 7 950ns monitor: a= 5 b= 3 sum=-8 1000ns monitor: a= 5 b= 4 sum=-7 1050ns monitor: a= 5 b= 5 sum=-6 1100ns monitor: a= 5 b= 6 sum=-5 1150ns monitor: a= 5 b= 7 sum=-4 1200ns monitor: a= 5 b=-8 sum=-3 1250ns monitor: a= 5 b=-7 sum=-2 1300ns monitor: a= 5 b=-6 sum=-1 1350ns monitor: a= 5 b=-5 sum= 0 1400ns monitor: a= 5 b=-4 sum= 1 1450ns monitor: a= 5 b=-3 sum= 2 1500ns monitor: a= 5 b=-2 sum= 3 1550ns monitor: a= 5 b=-1 sum= 4 1600ns monitor: a= 5 b= 0 sum= 5 1650ns monitor: a= 5 b= 1 sum= 6 1700ns monitor: a= 5 b= 2 sum= 7 1750ns monitor: a= 5 b= 3 sum=-8 1800ns monitor: a= 5 b= 4 sum=-7 1850ns monitor: a= 5 b= 5 sum=-6 1900ns monitor: a= 5 b= 6 sum=-5 1950ns monitor: a= 5 b= 7 sum=-4 2000ns monitor: a= 5 b=-8 sum=-3 無號數的加法 程式：adder4.v module fulladder (input a, b, c_in, output sum, c_out); wire s1, c1, c2; xor g1(s1, a, b); xor g2(sum, s1, c_in); and g3(c1, a,b); and g4(c2, s1, c_in) ; xor g5(c_out, c2, c1) ; endmodule module adder4(input [3:0] a, input [3:0] b, input c_in, output [3:0] sum, output c_out); wire [3:0] c; fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ; fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ; fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ; fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ; endmodule module main; reg [3:0] a; reg [3:0] b; wire [3:0] sum; wire c_out; adder4 DUT (a, b, 1'b0, sum, c_out); initial begin a = 4'b0101; b = 4'b0000; end always #50 begin b=b+1; $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum); end initial #2000 $finish; endmodule Icarus 編譯執行 D:\ccc101\icarus\ccc>iverilog -o adder4 adder4.v D:\ccc101\icarus\ccc>vvp adder4 50ns monitor: a= 5 b= 1 sum= 6 100ns monitor: a= 5 b= 2 sum= 7 150ns monitor: a= 5 b= 3 sum= 8 200ns monitor: a= 5 b= 4 sum= 9 250ns monitor: a= 5 b= 5 sum=10 300ns monitor: a= 5 b= 6 sum=11 350ns monitor: a= 5 b= 7 sum=12 400ns monitor: a= 5 b= 8 sum=13 450ns monitor: a= 5 b= 9 sum=14 500ns monitor: a= 5 b=10 sum=15 550ns monitor: a= 5 b=11 sum= 0 600ns monitor: a= 5 b=12 sum= 1 650ns monitor: a= 5 b=13 sum= 2 700ns monitor: a= 5 b=14 sum= 3 750ns monitor: a= 5 b=15 sum= 4 800ns monitor: a= 5 b= 0 sum= 5 850ns monitor: a= 5 b= 1 sum= 6 900ns monitor: a= 5 b= 2 sum= 7 950ns monitor: a= 5 b= 3 sum= 8 1000ns monitor: a= 5 b= 4 sum= 9 1050ns monitor: a= 5 b= 5 sum=10 1100ns monitor: a= 5 b= 6 sum=11 1150ns monitor: a= 5 b= 7 sum=12 1200ns monitor: a= 5 b= 8 sum=13 1250ns monitor: a= 5 b= 9 sum=14 1300ns monitor: a= 5 b=10 sum=15 1350ns monitor: a= 5 b=11 sum= 0 1400ns monitor: a= 5 b=12 sum= 1 1450ns monitor: a= 5 b=13 sum= 2 1500ns monitor: a= 5 b=14 sum= 3 1550ns monitor: a= 5 b=15 sum= 4 1600ns monitor: a= 5 b= 0 sum= 5 1650ns monitor: a= 5 b= 1 sum= 6 1700ns monitor: a= 5 b= 2 sum= 7 1750ns monitor: a= 5 b= 3 sum= 8 1800ns monitor: a= 5 b= 4 sum= 9 1850ns monitor: a= 5 b= 5 sum=10 1900ns monitor: a= 5 b= 6 sum=11 1950ns monitor: a= 5 b= 7 sum=12 2000ns monitor: a= 5 b= 8 sum=13 參考文獻 http://stenlyho.blogspot.com/2008/08/fulladd.html 4 Bit Ripple Carry Adder Facebook 留言 Facebook Wikidot Post preview: Close preview or Sign in as Wikidot user (will not be published) - + Help: wiki text quick reference 授權 本網頁的作者、授權與引用方式 作者 陳鍾誠，於金門大學資訊工程系，電子郵件：wt.ude.uqn|ccc#wt.ude.uqn|ccc，網站：http://ccckmit.wikidot.com。 授權 本文採用創作共用 (Creative Common) 3.0 版的 姓名標示─非商業性─相同方式分享 授權條款，歡迎轉載或修改使用，但若做為商業使用時必須取得授權，引用本文時請參考下列格式。 中文版 (APA格式) 陳鍾誠 (20 Apr 2012 01:22)，(網頁標題) 4 位元加法器，(網站標題) 陳鍾誠的網站，取自 http://ccckmit.wikidot.com/ve:adder4 ，網頁修改第 5 版。 英文版 (APA格式) Chung-Chen Chen (20 Apr 2012 01:22), Retrieved from http://ccckmit.wikidot.com/ve:adder4 , Page Revision 5.