#include<stdio.h> #include<stdlib.h> typedef long INT32; typedef unsigned short int INT16; typedef unsigned char BYTE; typedef struct BMP { // Header INT16 signature; // = "BM"; INT32 fileSize; INT32 hreserved; INT32 dataOffset; // InfoHeader INT32 size; INT32 width; INT16 height; INT16 planes; INT16 bitCount; INT32 compression; INT32 imageSize; INT32 xpixelsPerM; INT32 colorUsed; INT32 colorsImportant; // ColorTable BYTE blue; BYTE green; BYTE red; BYTE creserved; // Raster Data BYTE *image; } #define UCH(x) ((int) (x)) #define GET_2B(array,offset) ((INT16) UCH(array[offset]) + \ (((INT16) UCH(array[offset+1])) << 8)) #define GET_4B(array,offset) ((INT32) UCH(array[offset]) + \ (((INT32) UCH(array[offset+1])) << 8) + \ (((INT32) UCH(array[offset+2])) << 16) + \ (((INT32) UCH(array[offset+3])) << 24)) #define FREAD(file,buf,sizeofbuf) \ ((size_t) fread((void *) (buf), (size_t) 1, (size_t) (sizeofbuf), (file))) int bmpLoad(BMP *bmp, char *fileName) { FILE *file; BYTE header[14] = { 0 } ; BYTE info[40] = { 0 } ; if( (file = fopen(fileName, "rb") ) == NULL ){ fprintf(stderr, "Error: loadBmp(), File open fail!\n"); exit(0); } FREAD(file, header,14); FREAD(file, info,40); bmp->fileSize = GET_4B(header,2); bmp->dataOffset = GET_4B(header,10); bmp->size = GET_4B(info,0); bmp->width = GET_4B(info,4); bmp->height = GET_4B(info,8); bmp->planes = GET_2B(info,12); bmp->bitCount = GET_2B(info,14); bmp->biCompression = GET_4B(info,16); bmp->biImageSize = GET_4B(info,20); bmp->biXPelsPerMeter = GET_4B(info,24); bmp->biYPelsPerMeter = GET_4B(info,28); bmp->biClrUsed = GET_4B(info,32); bmp->biClrImp = GET_4B(info,36); fclose (input_file); } int bmpPrint(BMP *bmp) { printf("==== Header ====\n"); printf("FileSize = %ld \n", bmp->fileSize); printf("DataOffset = %ld \n", bmp->dataOffset); printf("==== Info ======\n"); printf("size = %ld \n", bmp->size); printf("Width = %ld \n", bmp->wize); printf("Height = %ld \n", bmp->height); printf("Planes = %d \n", bmp->planes); printf("BitCount = %d \n", bmp->bitCount); printf("Compression = %ld \n", bmp->compression); printf("ImageSize = %ld \n", bmp->imageSize); printf("XpixelsPerM = %ld \n", bmp->xPixelsPerM); printf("YpixelsPerM = %ld \n", bmp->yPixelsPerM); printf("ColorsUsed = %ld \n", bmp->colorsUsed); printf("ColorsImportant = %ld \n", bmp->colorsImportant); } int bmpSave(BMP *bmp, char *fileName) { } int main() { BMP bmp; bmpLoad(&bmp, "test.bmp"); bmpPrint(&bmp); return 0; } 

 E=T + T T=F * F T=3 

 D:\ccc101\CL>gcc gexp.c -o gexp D:\ccc101\CL>gexp 3*3+3*3 

 E=T [+-] T T=F [*/] F T=[0-9] 

 D:\ccc101\CL>gcc gexpr.c -o gexpr D:\ccc101\CL>gexpr 1/4+9*8 8*4-5/7 1/5+7*1 4*3+2/6 8/7+1*9 2/9-4/1 2/3+1/3 8/4+7/9 3/9+6/0 2*6+2*8 

 E=T ([+-] T)* T=F ([*/] F)? T=[0-9] 

 D:\ccc101\CL>gcc gexpr2.c -o gexpr2 D:\ccc101\CL>gexpr2 1 0 8+5/7-5/6+2*2+8/6+9/9 4/2 3/1 8 2 9/9 6*2 6*4 

 E=T ([+-] T)* T=F ([*/] F)? T=[0-9] | (E) 

 D:\ccc101\CL>gcc gexpr3.c -o gexpr3 D:\ccc101\CL>gexpr3 7*(8+5/1)-1*2-8/1(7)/2 4/8 2 (1)/2 0*(5/0)-((4*6)*9)/((9/9)*6) 5*9 7*1 7*2+4*1 7 5 

 #include "rlib.c" // === EBNF Grammar ===== // E=T [+-] T // T=F [*/] F // T=[0-9] int main(int argc, char * argv[]) { int i; for (i=0; i<10; i++) { E(); printf("\n"); } } int E() { T(); printf("%c", randChar("+-")); T(); } int T() { F(); printf("%c", randChar("*/")); F(); } int F() { printf("%c", randChar("0123456789")); } 

 D:\ccc101\CL>gcc gexpr.c -o gexpr D:\ccc101\CL>gexpr 1/4+9*8 8*4-5/7 1/5+7*1 4*3+2/6 8/7+1*9 2/9-4/1 2/3+1/3 8/4+7/9 3/9+6/0 2*6+2*8 

 #include <stdio.h> // === EBNF Grammar ===== // E=T + T // T=F * F // T=3 int main(int argc, char * argv[]) { E(); } int E() { T(); printf("+"); T(); } int T() { F(); printf("*"); F(); } int F() { printf("3"); } 

 D:\ccc101\CL>gcc gexp.c -o gexp D:\ccc101\CL>gexp 3*3+3*3 

 總結一下我對於十二年國教有以下的疑慮： (1)現在的制度就已經使很多的孩子並不一定要進明星高中，甚至於不進高中，進高職也是很多 年輕學子的願望。為什麼我們又要改革我們的制度呢？ (2)新的制度之下，十分有野心的學生絕對更加用功，因為明星學校的名額少了，而且他們要想 進私立高中，這些高中都是要考的。 (3)實施混材教育，將很會讀書的孩子和學習得很慢的孩子放在同一個教室，對於這些程度差的 學生來說，將是非常嚴重的打擊，他們一定會被放棄掉。所以，對弱勢孩子而言，他們未蒙其利 ，反而可能會受其害。 (4)對於絕大多數中等程度的同學而言，他們發現用不用功沒有多大的關係，最後到底能夠進哪 一所學校，絕對不是因為程度的關係。所以，他們會比現在還要不用功，整個國家的競爭力一定 會大幅下降。 (5)免試升學所要參考的項目，在我看來是非常不合理的，一個學生十分內向，不願意做幹部， 也不肯參加社團，為什麼在入學上要受到打擊？一個孩子體能不好，為什麼要受到打擊？ (6)免試升學考慮的項目複雜無比，會使家長有無力感和不確定感，也一定會使家長感到孩子 受到不公平的待遇。。 (7)我認為我們的惡補情況不會改善，恐怕還會加劇，至少現在已經有補習班要開“健康體 適能”的課程了。 

 李教授您好： 我發現一個現象！ 在民主社會中，由於每個人的主張不同，當我們針對某個主張大聲疾呼時，會造成 政府注意到這個問題，然後提出對應的「解決之道」。 但是目前的政府注重「民粹式的民意」，於是那些對選票沒有影響的民意就被忽略了， 而真正有影響力的，是那些具有「選票意義的民意」。 像是「全國家長聯盟」的意見就往往會逼得教育部做出反應，但是教育部的反應最後 只會是「討好選民式的反應」，這就造成了「今日的 12 年國教版本」。 我們的下一代，恐怕得在您說的環境下成長了。 而我們這一代，也只能「想辦法應付式的在體制下求存活」。 先前我不斷呼籲「不要只注重論文，技職體系高教化是不好的」，然而由於大學評鑑 的影響，現在我們只能想辦法去做出一堆文件來，應付大學評鑑與 IEET 工程認證。 大學老師們困在文件製作上，不只無法在技術上突破，連要寫論文的時間也沒了。 平庸，似乎已經成了我們的宿命！ 金門大學 陳鍾誠 

 module memory(input clock, reset, en, rw, input [31:0] abus, input [31:0] dbus_in, output [31:0] dbus_out); reg [7:0] m [0:128]; reg [31:0] data; always @(clock or reset or abus or en or rw or dbus_in) begin if (reset == 1) begin {m[0],m[1],m[2],m[3]} = 32'h002F000C; // 0000 LD R2, K0 {m[4],m[5],m[6],m[7]} = 32'h001F000C; // 0004 LD R1, K1 {m[8],m[9],m[10],m[11]} = 32'h13221000; // 0008 LOOP: ADD R2, R2, R1 {m[12],m[13],m[14],m[15]} = 32'h26FFFFF8; // 000C JMP LOOP {m[16],m[17],m[18],m[19]} = 32'h00000000; // 0010 K0: WORD 0 {m[20],m[21],m[22],m[23]} = 32'h00000001; // 0014 K1: WORD 1 data = 32'hZZZZZZZZ; end else if (abus >=0 && abus < 128) begin if (en == 1 && rw == 0) // r_w==0:write begin data = dbus_in; {m[abus], m[abus+1], m[abus+2], m[abus+3]} = dbus_in; end else if (en == 1 && rw == 1) // r_w==1:read data = {m[abus], m[abus+1], m[abus+2], m[abus+3]}; else data = 32'hZZZZZZZZ; end else data = 32'hZZZZZZZZ; end assign dbus_out = data; endmodule module main; reg clock, reset, en, rw; reg [31:0] addr; reg [31:0] data_in; wire [31:0] data_out; memory DUT (.clock(clock), .reset(reset), .en(en), .rw(rw), .abus(addr), .dbus_in(data_in), .dbus_out(data_out)); initial // reset：設定 memory 內容為 0,1,2,....,127 begin clock = 0; reset = 1; en = 0; rw = 1; // rw=1:讀取模式 #75; en = 1; reset = 0; addr = 0; #500; addr = 4; rw = 0; // 寫入模式 data_in = 8'h3A; #100; addr = 0; rw = 1; // 讀取模式 data_in = 0; end always #50 begin clock = clock + 1; $monitor("%4dns monitor: clk=%d en=%d rw=%d, addr=%8h din=%8h dout=%8h", $stime, clock, en, rw, addr, data_in, data_out); end always #200 begin addr=addr+1; end initial #2000 $finish; endmodule 

 D:\ccc101\Verilog>iverilog mem32.v -o mem32 D:\ccc101\Verilog>vvp mem32 50ns monitor: clk=1 en=0 rw=1, addr=xxxxxxxx din=xxxxxxxx dout=zzzzzzzz 75ns monitor: clk=1 en=1 rw=1, addr=00000000 din=xxxxxxxx dout=002f000c 100ns monitor: clk=0 en=1 rw=1, addr=00000000 din=xxxxxxxx dout=002f000c 150ns monitor: clk=1 en=1 rw=1, addr=00000000 din=xxxxxxxx dout=002f000c 200ns monitor: clk=0 en=1 rw=1, addr=00000001 din=xxxxxxxx dout=2f000c00 250ns monitor: clk=1 en=1 rw=1, addr=00000001 din=xxxxxxxx dout=2f000c00 300ns monitor: clk=0 en=1 rw=1, addr=00000001 din=xxxxxxxx dout=2f000c00 350ns monitor: clk=1 en=1 rw=1, addr=00000001 din=xxxxxxxx dout=2f000c00 400ns monitor: clk=0 en=1 rw=1, addr=00000002 din=xxxxxxxx dout=000c001f 450ns monitor: clk=1 en=1 rw=1, addr=00000002 din=xxxxxxxx dout=000c001f 500ns monitor: clk=0 en=1 rw=1, addr=00000002 din=xxxxxxxx dout=000c001f 550ns monitor: clk=1 en=1 rw=1, addr=00000002 din=xxxxxxxx dout=000c001f 575ns monitor: clk=1 en=1 rw=0, addr=00000004 din=0000003a dout=0000003a 600ns monitor: clk=0 en=1 rw=0, addr=00000005 din=0000003a dout=0000003a 650ns monitor: clk=1 en=1 rw=0, addr=00000005 din=0000003a dout=0000003a 675ns monitor: clk=1 en=1 rw=1, addr=00000000 din=00000000 dout=002f000c 700ns monitor: clk=0 en=1 rw=1, addr=00000000 din=00000000 dout=002f000c 750ns monitor: clk=1 en=1 rw=1, addr=00000000 din=00000000 dout=002f000c 800ns monitor: clk=0 en=1 rw=1, addr=00000001 din=00000000 dout=2f000c00 850ns monitor: clk=1 en=1 rw=1, addr=00000001 din=00000000 dout=2f000c00 900ns monitor: clk=0 en=1 rw=1, addr=00000001 din=00000000 dout=2f000c00 950ns monitor: clk=1 en=1 rw=1, addr=00000001 din=00000000 dout=2f000c00 1000ns monitor: clk=0 en=1 rw=1, addr=00000002 din=00000000 dout=000c0000 1050ns monitor: clk=1 en=1 rw=1, addr=00000002 din=00000000 dout=000c0000 1100ns monitor: clk=0 en=1 rw=1, addr=00000002 din=00000000 dout=000c0000 1150ns monitor: clk=1 en=1 rw=1, addr=00000002 din=00000000 dout=000c0000 1200ns monitor: clk=0 en=1 rw=1, addr=00000003 din=00000000 dout=0c000000 1250ns monitor: clk=1 en=1 rw=1, addr=00000003 din=00000000 dout=0c000000 1300ns monitor: clk=0 en=1 rw=1, addr=00000003 din=00000000 dout=0c000000 1350ns monitor: clk=1 en=1 rw=1, addr=00000003 din=00000000 dout=0c000000 1400ns monitor: clk=0 en=1 rw=1, addr=00000004 din=00000000 dout=00000000 1450ns monitor: clk=1 en=1 rw=1, addr=00000004 din=00000000 dout=00000000 1500ns monitor: clk=0 en=1 rw=1, addr=00000004 din=00000000 dout=00000000 1550ns monitor: clk=1 en=1 rw=1, addr=00000004 din=00000000 dout=00000000 1600ns monitor: clk=0 en=1 rw=1, addr=00000005 din=00000000 dout=0000003a 1650ns monitor: clk=1 en=1 rw=1, addr=00000005 din=00000000 dout=0000003a 1700ns monitor: clk=0 en=1 rw=1, addr=00000005 din=00000000 dout=0000003a 1750ns monitor: clk=1 en=1 rw=1, addr=00000005 din=00000000 dout=0000003a 1800ns monitor: clk=0 en=1 rw=1, addr=00000006 din=00000000 dout=00003a22 1850ns monitor: clk=1 en=1 rw=1, addr=00000006 din=00000000 dout=00003a22 1900ns monitor: clk=0 en=1 rw=1, addr=00000006 din=00000000 dout=00003a22 1950ns monitor: clk=1 en=1 rw=1, addr=00000006 din=00000000 dout=00003a22 2000ns monitor: clk=0 en=1 rw=1, addr=00000007 din=00000000 dout=003a2210 

 module memory(input clock, reset, en, r_w, input [7:0] abus, input [7:0] dbus_in, output [7:0] dbus_out); reg [7:0] m [0:128]; reg [7:0] data; reg [7:0] i; always @(posedge clock) begin if (reset == 1) begin m[0] <= 8'h00; m[1] <= 8'h01; m[2] <= 8'h02; m[3] <= 8'h03; m[4] <= 8'h04; data = 8'h00; end else if (en == 1 && r_w == 0) // r_w==0:write begin data = dbus_in; m[abus] = dbus_in; end else if (en == 1 && r_w == 1) // r_w==1:read data = m[abus]; else data = 8'hZZ; end assign dbus_out = data; endmodule 

 `timescale 1ns/10ps module memoryTest; reg clock, reset, en, r_w; reg [7:0] addr; reg [7:0] data_in; wire [7:0] dbus_out; memory DUT (.clock(clock), .reset(reset), .en(en), .r_w(r_w), .abus(addr), .dbus_in(data_in), .dbus_out(dbus_out)); initial // reset：設定 memory 內容為 0,1,2,....,127 begin clock = 0; reset = 1; en = 0; r_w = 1; // r_w=1:讀取模式 #75; en = 1; reset = 0; addr = 0; #500; addr = 1; r_w = 0; // 寫入模式 data_in = 8'h3A; #100; addr = 0; r_w = 1; // 讀取模式 data_in = 0; end always #50 clock = clock + 1; always #200 begin addr=addr+1; end endmodule 

 module ram(input clock, reset, en, r_w, input [7:0] abus, inout [7:0] dbus); reg [7:0] m [0:128]; reg [7:0] data; reg [7:0] i; always @(posedge clock) begin if (reset == 1) begin m[0] <= 8'h00; m[1] <= 8'h01; m[2] <= 8'h02; m[3] <= 8'h03; m[4] <= 8'h04; data = 8'hZZ; end else if (en == 1 && r_w == 0) // r_w==0:write begin data = dbus; m[abus] = dbus; end else if (en == 1 && r_w == 1) // r_w==1:read data = m[abus]; else data = 8'hZZ; end assign dbus = data; endmodule 

 `timescale 1ns/10ps module ramTest; reg clock, reset, en, r_w; reg [7:0] addr; wire [7:0] dbus; ram DUT (.clock(clock), .reset(reset), .en(en), .r_w(r_w), .abus(addr), .dbus(dbus)); initial // reset：設定 memory 內容為 0,1,2,....,127 begin $display ("ramTest:initial"); clock = 0; reset = 1; en = 0; r_w = 1; // r_w=1:讀取模式 #100; en = 1; reset = 0; addr = 0; end always #50 clock = clock + 1; always #200 begin addr=addr+1; end endmodule 

 module mema (r_wb,addr,d_q); input r_wb; input [7:0] addr; inout [7:0] d_q; reg [7:0] data [0:255]; assign d_q = (r_wb) ? data[addr] : 8'hz ; always @(r_wb) if (!r_wb) data[addr] = d_q ; always @(addr) if (!r_wb) data[addr] = d_q ; endmodule 

 module i2c_sp_ram( //Inputs clk, //clock wr_en, //write enable rd_en, //read enable addr, //address data_in,//data in //Output data_out//data out ); //Parameter Declaration parameter DEPTH = 8; //depth of FIFO parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width parameter DATA_BUS_WD = 8; //data bus width //Inputs Declarations input clk; //Clock input wr_en; //Write Enable input rd_en; //Read Enable input [ADDR_BUS_WD-1:0] addr; //Address Width input [DATA_BUS_WD-1:0] data_in; //Data Input //output Declarations output [DATA_BUS_WD-1:0] data_out; //Data Output //reg Declarations reg [DATA_BUS_WD-1:0] mem [DEPTH-1:0];//Memory reg [DATA_BUS_WD-1:0] data_out; //Data Output //Generation of data_out always @(posedge clk) begin : READ_GEN if(rd_en) data_out <= mem[addr]; end //Generation Writing data into memory always @(posedge clk) begin: WRITE_GEN if(wr_en) mem[addr] <= data_in; end endmodule 

 module RamChip (Address, Data, CS, WE, OE); parameter AddressSize = 1; parameter WordSize = 1; input [AddressSize-1:0] Address; inout [WordSize-1:0] Data; input CS, WE, OE; reg [WordSize-1:0] Mem [0:1<<AddressSize]; assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}}; always @(CS or WE) if (!CS && !WE) Mem[Address] = Data; always @(WE or OE) if (!WE && !OE) $display("Operational error in RamChip: OE and WE both active"); endmodule 

 `timescale 10ns/1ns module ptd(input clk, output ppulse); not g1(nclkd, clk); nand g2(npulse, nclkd, clk); not g3(ppulse, npulse); endmodule module register(input en, input [31:0] d, output reg [31:0] r); always @(en) begin r <= d; end endmodule module main; reg [31:0] d; wire [31:0] r; reg clk; wire en; ptd ptd1(clk, en); register register1(en, d, r); initial begin clk = 0; d = 3; end always #1 begin $monitor("%4dns monitor: clk=%d en=%d d=%d r=%d", $stime, clk, en, d, r); end always #10 begin clk = clk + 1; end always #20 begin d = d + 1; end initial #100 $finish; endmodule 

 D:\ccc101\Verilog>iverilog ptdRegister.v -o ptdRegister D:\ccc101\Verilog>vvp ptdRegister 1ns monitor: clk=0 en=0 d= 3 r= 3 2ns monitor: clk=0 en=0 d= 3 r= 3 3ns monitor: clk=0 en=0 d= 3 r= 3 4ns monitor: clk=0 en=0 d= 3 r= 3 5ns monitor: clk=0 en=0 d= 3 r= 3 6ns monitor: clk=0 en=0 d= 3 r= 3 7ns monitor: clk=0 en=0 d= 3 r= 3 8ns monitor: clk=0 en=0 d= 3 r= 3 9ns monitor: clk=0 en=0 d= 3 r= 3 10ns monitor: clk=1 en=0 d= 3 r= 3 11ns monitor: clk=1 en=0 d= 3 r= 3 12ns monitor: clk=1 en=0 d= 3 r= 3 13ns monitor: clk=1 en=0 d= 3 r= 3 14ns monitor: clk=1 en=0 d= 3 r= 3 15ns monitor: clk=1 en=0 d= 3 r= 3 16ns monitor: clk=1 en=0 d= 3 r= 3 17ns monitor: clk=1 en=0 d= 3 r= 3 18ns monitor: clk=1 en=0 d= 3 r= 3 19ns monitor: clk=1 en=0 d= 3 r= 3 20ns monitor: clk=0 en=0 d= 4 r= 3 21ns monitor: clk=0 en=0 d= 4 r= 3 22ns monitor: clk=0 en=0 d= 4 r= 3 23ns monitor: clk=0 en=0 d= 4 r= 3 24ns monitor: clk=0 en=0 d= 4 r= 3 25ns monitor: clk=0 en=0 d= 4 r= 3 26ns monitor: clk=0 en=0 d= 4 r= 3 27ns monitor: clk=0 en=0 d= 4 r= 3 28ns monitor: clk=0 en=0 d= 4 r= 3 29ns monitor: clk=0 en=0 d= 4 r= 3 30ns monitor: clk=1 en=0 d= 4 r= 4 31ns monitor: clk=1 en=0 d= 4 r= 4 32ns monitor: clk=1 en=0 d= 4 r= 4 33ns monitor: clk=1 en=0 d= 4 r= 4 34ns monitor: clk=1 en=0 d= 4 r= 4 35ns monitor: clk=1 en=0 d= 4 r= 4 36ns monitor: clk=1 en=0 d= 4 r= 4 37ns monitor: clk=1 en=0 d= 4 r= 4 38ns monitor: clk=1 en=0 d= 4 r= 4 39ns monitor: clk=1 en=0 d= 4 r= 4 40ns monitor: clk=0 en=0 d= 5 r= 4 41ns monitor: clk=0 en=0 d= 5 r= 4 42ns monitor: clk=0 en=0 d= 5 r= 4 43ns monitor: clk=0 en=0 d= 5 r= 4 44ns monitor: clk=0 en=0 d= 5 r= 4 45ns monitor: clk=0 en=0 d= 5 r= 4 46ns monitor: clk=0 en=0 d= 5 r= 4 47ns monitor: clk=0 en=0 d= 5 r= 4 48ns monitor: clk=0 en=0 d= 5 r= 4 49ns monitor: clk=0 en=0 d= 5 r= 4 50ns monitor: clk=1 en=0 d= 5 r= 5 51ns monitor: clk=1 en=0 d= 5 r= 5 52ns monitor: clk=1 en=0 d= 5 r= 5 53ns monitor: clk=1 en=0 d= 5 r= 5 54ns monitor: clk=1 en=0 d= 5 r= 5 55ns monitor: clk=1 en=0 d= 5 r= 5 56ns monitor: clk=1 en=0 d= 5 r= 5 57ns monitor: clk=1 en=0 d= 5 r= 5 58ns monitor: clk=1 en=0 d= 5 r= 5 59ns monitor: clk=1 en=0 d= 5 r= 5 60ns monitor: clk=0 en=0 d= 6 r= 5 61ns monitor: clk=0 en=0 d= 6 r= 5 62ns monitor: clk=0 en=0 d= 6 r= 5 63ns monitor: clk=0 en=0 d= 6 r= 5 64ns monitor: clk=0 en=0 d= 6 r= 5 65ns monitor: clk=0 en=0 d= 6 r= 5 66ns monitor: clk=0 en=0 d= 6 r= 5 67ns monitor: clk=0 en=0 d= 6 r= 5 68ns monitor: clk=0 en=0 d= 6 r= 5 69ns monitor: clk=0 en=0 d= 6 r= 5 70ns monitor: clk=1 en=0 d= 6 r= 6 71ns monitor: clk=1 en=0 d= 6 r= 6 72ns monitor: clk=1 en=0 d= 6 r= 6 73ns monitor: clk=1 en=0 d= 6 r= 6 74ns monitor: clk=1 en=0 d= 6 r= 6 75ns monitor: clk=1 en=0 d= 6 r= 6 76ns monitor: clk=1 en=0 d= 6 r= 6 77ns monitor: clk=1 en=0 d= 6 r= 6 78ns monitor: clk=1 en=0 d= 6 r= 6 79ns monitor: clk=1 en=0 d= 6 r= 6 80ns monitor: clk=0 en=0 d= 7 r= 6 81ns monitor: clk=0 en=0 d= 7 r= 6 82ns monitor: clk=0 en=0 d= 7 r= 6 83ns monitor: clk=0 en=0 d= 7 r= 6 84ns monitor: clk=0 en=0 d= 7 r= 6 85ns monitor: clk=0 en=0 d= 7 r= 6 86ns monitor: clk=0 en=0 d= 7 r= 6 87ns monitor: clk=0 en=0 d= 7 r= 6 88ns monitor: clk=0 en=0 d= 7 r= 6 89ns monitor: clk=0 en=0 d= 7 r= 6 90ns monitor: clk=1 en=0 d= 7 r= 7 91ns monitor: clk=1 en=0 d= 7 r= 7 92ns monitor: clk=1 en=0 d= 7 r= 7 93ns monitor: clk=1 en=0 d= 7 r= 7 94ns monitor: clk=1 en=0 d= 7 r= 7 95ns monitor: clk=1 en=0 d= 7 r= 7 96ns monitor: clk=1 en=0 d= 7 r= 7 97ns monitor: clk=1 en=0 d= 7 r= 7 98ns monitor: clk=1 en=0 d= 7 r= 7 99ns monitor: clk=1 en=0 d= 7 r= 7 100ns monitor: clk=0 en=0 d= 8 r= 7 

 `timescale 10ns/1ns module ptd(input clk, output ppulse); not g1(nclkd, clk); nand g2(npulse, nclkd, clk); not g3(ppulse, npulse); endmodule