程式計數模組

Verilog 程式碼:pcTick.v

module pcTick(input clock, reset, output reg [31:0] pc, 
             output reg [2:0] tick);
    always @(posedge clock) begin
        if (reset) 
          begin
            pc = 0;
            tick = 0;
          end
        else begin
            tick = tick+1;
            if (tick == 6) begin
                tick = 0;
                pc = pc+4;
            end
            $monitor("%4dns %8x %1x", $stime, pc, tick);
        end
    end
endmodule

module main;
reg clock;
reg reset;
wire [2:0] tick;
wire [31:0] pc;

pcTick DUT (.clock(clock), .reset(reset), .pc(pc), .tick(tick));

initial
begin
  clock = 0;
  reset = 1;
  #100 reset=0;
  #2000 $finish;
end

always #50 clock=clock+1;
endmodule

Icarus 執行結果

D:\oc\cpu0m>iverilog pcTick.v -o pcTick

D:\oc\cpu0m>vvp pcTick
 150ns 00000000 1
 250ns 00000000 2
 350ns 00000000 3
 450ns 00000000 4
 550ns 00000000 5
 650ns 00000004 0
 750ns 00000004 1
 850ns 00000004 2
 950ns 00000004 3
1050ns 00000004 4
1150ns 00000004 5
1250ns 00000008 0
1350ns 00000008 1
1450ns 00000008 2
1550ns 00000008 3
1650ns 00000008 4
1750ns 00000008 5
1850ns 0000000c 0
1950ns 0000000c 1
2050ns 0000000c 2
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