控制單元

CPU0 處理器

基礎知識

Verilog

程式計數模組

記憶體

指令提取單元

跳躍指令

控制單元

CPU0-Mini

CPU0

DE2-70 板實作

LED 與開關

七段顯示器

Clock 時脈

程式計數器

跳躍指令

CPU0-Mini

CPU0

Icarus 實作

CPU0-Mini

訊息

相關網站

參考文獻

最新修改

簡體版

English

指令提取階段

時脈 0: abus = PC
時脈 1: IR = dbus
時脈 2: PC = PC + 4
時脈 3:
時脈 4:
時脈 5:

主要模組

module computer0m(input clock, reset, output [31:0] pc, 
             output [2:0] tick, output [31:0] ir,
                 output [31:0] mar, output [31:0] mdr,
                 inout [31:0] dbus, output m_en, m_rw);

cpu0m cpu (.clock(clock), .reset(reset), .pc(pc), .tick(tick), .ir(ir), 
.mar(mar), .mdr(mdr), .dbus(dbus), .m_en(m_en), .m_rw(m_rw));

memory0m mem (.clock(clock), .reset(reset), .en(m_en), .rw(m_rw), 
.abus(mar), .dbus_in(dbus), .dbus_out(dbus));

endmodule         

module cpu0m(input clock, reset, output reg [31:0] pc, 
             output reg [2:0] tick, output reg [31:0] ir,
                 output reg [31:0] mar, output reg [31:0] mdr,
                 inout [31:0] dbus, output reg m_en, m_rw);
    always @(posedge clock) begin
        if (reset) 
          begin
            pc = 0;
            tick = 0;
            m_en = 1;
          end
        else begin
            tick = tick+1;
            case (tick)
                1:
                begin // memory.read(m[PC])
                    mar = pc; // MAR = PC
                    m_rw = 1; // m_rw=1 is read mode, read(m[MAR]) => read(m[PC])
                end
                2: 
                begin
                    mdr = dbus;
                    ir = mdr; // IR = dbus = m[PC]
                end
                3:
                begin
                    pc = pc+1;
                end
                4:
                begin
                end
                5:
                begin
                end
                6:
                begin
                    tick = 0;
                end
                default:
                begin
                end
            endcase
        end
    end

endmodule

module memory0m(input clock, reset, en, rw, 
            input [31:0] abus, input [31:0] dbus_in, output [31:0] dbus_out);
reg [31:0] m [0:128];
reg [31:0] data;

    always @(clock or reset or abus or en or rw or dbus_in) 
    begin
        if (reset == 1) begin
            m[0] <= 32'h00100010;
            m[1] <= 32'h0110000C; 
            m[2] <= 32'h2C000000;  
            m[3] <= 32'h00000000; 
            m[4] <= 32'h0000001D; 
            data <= 32'hZZZZZZZZ;
        end else if (abus >=0 && abus < 128) begin
            if (en == 1 && rw == 0) // r_w==0:write
            begin
                data <= dbus_in;
                m[abus] <= dbus_in;
            end
            else if (en == 1 && rw == 1) // r_w==1:read
                data <= m[abus];
            else
                data <= 32'hZZZZZZZZ;
        end else
            data <= 32'hZZZZZZZZ;
    end
    assign dbus_out = data;
endmodule

測試程式

`timescale 1ns/10ps

module computer0mTest;
reg clock;
reg reset;
wire [2:0] tick;
wire [31:0] pc;
wire [31:0] ir;
wire [31:0] mar;
wire [31:0] mdr;
wire [31:0] dbus;
wire m_en, m_rw;

computer0m DUT (.clock(clock), .reset(reset), .pc(pc), .tick(tick), .ir(ir), 
.mar(mar), .mdr(mdr), .dbus(dbus), .m_en(m_en), .m_rw(m_rw));

initial
begin
  clock = 0;
  reset = 1;
end

initial #100 reset = 0;

always #50 clock=clock+1;

endmodule

執行結果

computer0mRun.jpg

參考文獻

  1. http://en.wikipedia.org/wiki/Microcode

Facebook

Unless otherwise stated, the content of this page is licensed under Creative Commons Attribution-NonCommercial-ShareAlike 3.0 License