Altera DE2-70 的程式計數器模組實作

Verilog 程式

``````module Computer0m(input clock, reset,
output [0:7] segPc1, output [0:7] segPc0, output [0:7] segTick);
wire [31:0] counter;
wire [31:0] pc;
wire [3:0] tick;

Counter mCounter(clock, counter);
PcTick mPcTick(counter[25], reset, pc, tick);
Seg7 mSegPc1(pc[7:4], segPc1);
Seg7 mSegPc0(pc[3:0], segPc0);
Seg7 mSegTick(tick, segTick);

endmodule

module PcTick(input clock, reset, output reg [31:0] pc,
output reg [2:0] tick);
always @(posedge clock) begin
if (reset)
begin
pc = 0;
tick = 0;
end
else begin
tick = tick+1;
if (tick == 6) begin
tick = 0;
pc = pc+4;
end
end
end
endmodule

module Seg7(input [3:0] num, output [0:7] seg);
reg [7:0] nseg;
always @(num) begin
case (num)
4'b0000: nseg = 8'b11111100; // 0
4'b0001: nseg = 8'b01100000; // 1
4'b0010: nseg = 8'b11011010; // 2
4'b0011: nseg = 8'b11110010; // 3
4'b0100: nseg = 8'b01100110; // 4
4'b0101: nseg = 8'b10110110; // 5
4'b0110: nseg = 8'b10111110; // 6
4'b0111: nseg = 8'b11100100; // 7
4'b1000: nseg = 8'b11111110; // 8
4'b1001: nseg = 8'b11110110; // 9
4'b1010: nseg = 8'b11101110; // A
4'b1011: nseg = 8'b00111110; // b
4'b1100: nseg = 8'b10011100; // C
4'b1101: nseg = 8'b01111010; // d
4'b1110: nseg = 8'b10011110; // E
4'b1111: nseg = 8'b10001110; // F
default: nseg = 8'b00000000; //
endcase
end
assign seg = ~nseg;
endmodule

module Counter(input clock, output reg [31:0] counter);
always @(posedge clock) begin
counter = counter + 1;
end
endmodule```
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